Cache Line Multi-Bit Error Correction for Ultra-Low Voltage
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Solution Overview
Problem
As semiconductor technology advances, reducing supply voltage to conserve energy leads to increased manufacturing-induced parameter variations, causing circuit failures and restricting voltage scaling, which hinders the implementation of ultra-low power modes in processors.
Innovation Solution
Implementing a multi-bit error correction technique using Orthogonal Latin Square Codes (OLSC) in the processor's memory subsystem, which partitions the cache into data and ECC ways, allowing for error correction at ultra-low voltage levels by encoding and decoding data segments separately, thereby enabling reliable operation at reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If supply voltage is reduced to conserve energy, then power consumption is reduced, but manufacturing-induced parameter variations increase causing circuit failures
Solution Approach 1:
The cache is divided into multiple ways, with selected ways designated as ECC ways for error correction and others as data ways for storage. This segmentation allows the system to maintain reliability through dedicated error correction resources while preserving performance through parallel data access paths.
Solution Approach 2:
ECC check bits are generated and stored in advance in the ECC ways before data is actually read or written. This preliminary encoding enables error correction to be performed quickly during data access without adding latency, as the correction logic is already prepared and can operate in parallel with data operations.
2Loss of energy
If supply voltage is reduced to enable ultra-low power mode, then energy efficiency improves, but manufacturing variations cause memory cell failures
Solution Approach 1:
The memory subsystem is segmented into data ways and ECC ways, allowing dedicated error correction resources to operate independently. This enables robust memory operation at ultra-low voltages where manufacturing variations would otherwise cause failures, while the data ways can be optimized for low-power operation.
Solution Approach 2:
Redundant ECC check bits are stored in advance in the ECC ways to cushion against potential errors that may occur during ultra-low voltage operation. This preparatory error correction capability protects against manufacturing variations and voltage-induced failures before they affect data integrity.
3Reliability
If traditional error correction is used at ultra-low voltage, then reliability may be maintained, but complexity and latency of error correction processes increase
Solution Approach 1:
By dividing the cache into data ways and ECC ways, the error correction complexity is isolated to dedicated ECC ways rather than being distributed across the entire cache. This segmentation allows simpler correction logic in each ECC way while maintaining overall system reliability.
Solution Approach 2:
ECC check bits are generated and stored in the ECC ways in advance, before data access operations occur. This preliminary action eliminates the need for complex real-time error correction during data reads and writes, reducing latency and simplifying the operational complexity of the memory subsystem.
4Use of energy by moving object
If supply voltage is reduced, then power consumption decreases, but performance may be compromised due to frequency reduction
Solution Approach 1:
The cache is segmented into data ways and ECC ways, enabling parallel operation where data ways can be accessed at full speed while ECC ways perform error correction independently. This segmentation allows the system to maintain high performance in data access paths while operating at reduced voltage for lower power consumption.
Solution Approach 2:
Error correction is performed in advance and stored in the ECC ways, so that during data access operations, no additional time is needed for error correction. This preliminary action eliminates performance penalties that would otherwise result from voltage-induced frequency reduction, allowing the processor to maintain high performance while consuming less power.
Data Source
AI summary
A processor may comprise a cache, which may be divided into a first and second section while the processor operates in a low-power mode. A cache line of the first section may be fragmented into segments. A first encoder may generate first data bits and check bits while encoding a first portion of a data stream and a second encoder may, separately, generate second data bits and check bits while encoding a second portion of the data stream. The first data bits may be stored in a first segment of the first section and the check bits in a first portion of the second section that is associated with the first segment. The first decoder may correct errors in multiple bit positions within the first data bits using the check bits stored in the first portion and the second decoder may, separately, decode the second data bits using the second set of check bits.