Cache Line Eviction Logic for Non-Uniform Miss Penalty Optimization
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Solution Overview
Problem
Current pseudo LRU cache replacement policies in microprocessor cache subsystems often result in suboptimal eviction choices due to the inability to precisely track cache line ages, leading to performance degradation and increased power consumption, as they may evict cache lines with better locality or those residing in more costly memory locations.
Innovation Solution
The implementation of a cache line eviction logic that considers the non-uniform cache miss penalty, selecting the cache line with the smallest miss penalty as the eviction victim, and randomly selecting from remaining candidates when multiple have similar penalties, to optimize cache management and reduce costly memory accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If pseudo LRU implementation is used to reduce hardware resources, then device complexity is reduced, but cache replacement accuracy deteriorates
Solution Approach 1:
The patent applies local quality by differentiating the treatment of cache lines based on their individual characteristics. Instead of uniform eviction, the system evaluates each cache line's miss penalty and selectively evicts only those with low miss penalties, preserving cache lines with high miss penalties even if they are least recently used. This localized decision-making resolves the contradiction by maintaining accuracy where it matters most (for costly cache lines) while accepting approximate behavior for less critical lines.
2Device complexity
If pseudo LRU implementation is used to reduce hardware resources, then device complexity is reduced, but processor performance deteriorates
Solution Approach 1:
The patent changes the evaluation parameter from单纯的最近使用时间 (time since last access) to a composite parameter that includes miss penalty. By incorporating miss penalty as an additional parameter in the eviction decision, the system achieves better performance without requiring full LRU hardware complexity. This parameter enrichment allows the pseudo LRU implementation to make more informed decisions, resolving the performance deterioration issue.
3Device complexity
If pseudo LRU implementation is used to reduce hardware resources, then device complexity is reduced, but power consumption increases
Solution Approach 1:
The patent applies local quality by evaluating each cache line's individual miss penalty and making targeted eviction decisions. Instead of uniformly evicting based on simple pseudo LRU, the system selectively evicts only cache lines with low miss penalties, avoiding the energy cost of fetching high penalty cache lines from remote memory. This localized optimization reduces overall power consumption while maintaining the simplicity of pseudo LRU hardware.
Data Source
AI summary
Method, system, and apparatus for leveraging non-uniform miss penalty in cache replacement policy to improve performance and power in a chip multiprocessor platform is described herein. One embodiment of a method includes: determining a first set of cache line candidates for eviction from a first memory in accordance to a cache line replacement policy, the first set comprising a plurality of cache line candidates; determining a second set of cache line candidates from the first set based on replacement penalties associated with each respective cache line candidate in the first set; selecting a target cache line from the second set of cache line candidates; and responsively causing the selected target cache line to be moved from the first memory to a second memory.