Cache Memory Line Fill Termination for Interrupt Latency
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Solution Overview
Problem
In embedded computer systems, the variability in interrupt latency can be significant due to cache memory operations, leading to unpredictable processor response times, which can result in system failures even with short average latency.
Innovation Solution
The system configures the data processor and cache memory subsystem to receive interrupt indications simultaneously, allowing the cache memory subsystem to prepare for interrupt-related requests by terminating cache line fills in response to interrupt indications, thereby reducing latency variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the cache memory subsystem completes filling a cache line before beginning another operation, then cache memory consistency is maintained, but interrupt latency increases when a cache line fill is in progress
Solution Approach 1:
The cache memory subsystem receives the interrupt indication before the processor and begins preparing for the interrupt in advance. This preliminary action allows the cache to terminate ongoing cache line fills and be ready for interrupt-related memory requests, reducing the actual interrupt latency when the processor needs to handle the interrupt.
Solution Approach 2:
The cache memory subsystem dynamically adjusts its operation based on the interrupt indication. When an interrupt is detected, the cache changes from completing cache line fills to terminating them and preparing for interrupt handling. This dynamic behavior allows the system to prioritize interrupt responses while maintaining cache consistency when interrupts are not present.
2Reliability
If the processor waits for cache line fill completion before executing interrupt handler code, then cache memory operations are completed properly, but interrupt response time increases
Solution Approach 1:
The cache memory subsystem performs preliminary actions by receiving and processing the interrupt indication before the processor. This allows the cache to terminate any ongoing cache line fills and be ready for the interrupt-related memory requests, so the processor does not need to wait for cache operations when handling interrupts.
Solution Approach 2:
The interrupt indication processing is extracted from the processor and handled separately by the cache memory subsystem. This separation allows the cache to prepare for interrupts independently, removing the dependency of interrupt response on cache line fill completion and reducing interrupt latency.
3Loss of time
If the cache memory subsystem terminates a cache line fill in response to an interrupt indication, then interrupt latency is reduced, but cache memory consistency may be affected
Solution Approach 1:
The cache memory subsystem receives the interrupt indication and terminates cache line fills in advance, before the processor needs to execute interrupt handler code. This preliminary termination reduces interrupt latency while maintaining consistency because the cache is prepared for the interrupt request without completing unnecessary cache line fills.
Data Source
AI summary
An embedded computer system includes a processor, an interrupt source, an interrupt controller and a cache memory subsystem. In response to a request from the processor to read a data element, the cache memory subsystem fills cache lines in a cache memory with data elements read from an upper-level memory. While filling a cache line the cache memory subsystem is unable to respond to a second request from the processor which also requires a cache line fill. In response to receiving an indication from an interrupt source, the interrupt controller provides an indication substantially simultaneously to the processor and to the cache memory subsystem. In response to receiving the indication from the interrupt controller, the cache memory subsystem terminates a cache line fill and prepares to receive another request from the processor.