Cache Line FLIT Packing to Reduce External-Link Transactions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Delays in cache line transfers due to separate transmission of data and metadata in processing systems slow down performance, complicating data coherency maintenance.
Innovation Solution
A conversion circuit generates flow control units (FLITs) that incorporate cache lines and associated metadata in a single transmission over external links, using protocols like PCIe and CXL, reducing the need for separate data and metadata transmissions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache lines and metadata are transmitted separately over external links, then transmission reliability is improved, but transmission latency increases and performance deteriorates
Solution Approach 1:
The patent combines cache line data and metadata into a single FLIT transmission unit. The conversion circuit packs both the cache line content and associated metadata (such as tag information, validity bits, and ownership status) into one unified flow control unit, eliminating the need for separate transmissions and reducing overall latency while maintaining data integrity
2Measurement precision
If separate transmissions are used for cache lines and metadata, then transmission accuracy is improved, but productivity decreases
Solution Approach 1:
The patent merges cache line and metadata into a single atomic transmission unit (FLIT), improving throughput by reducing the number of transactions. The unified structure ensures that both data and metadata arrive together, maintaining transmission accuracy while significantly boosting productivity through reduced overhead and fewer link traversals
Solution Approach 2:
The FLIT is segmented into distinct fields for cache line data and metadata, allowing the receiving device to process them efficiently as a unified unit while maintaining the ability to validate and handle each component appropriately, thus preserving accuracy while enhancing throughput
3Device complexity
If separate transmissions are used for cache lines and metadata, then device complexity is reduced, but performance deteriorates
Solution Approach 1:
The patent combines cache line and metadata into a single FLIT structure with a unified transmission protocol, reducing the number of protocol handshakes and transactions required. This merging simplifies the overall transmission process while dramatically improving performance through reduced latency and increased throughput
Data Source
AI summary
In a processing system, a conversion circuit coupled to a system bus generates a flow control unit (FLIT) and provides the FLIT to a link interface circuit for transmission over an external link. The external link may be a peripheral component interface (PCI) express (PCIe) link coupled to an external device comprising a cache or memory. The conversion circuit generates the FLIT, including write information based on the write instruction, metadata associated with at least one cache line, and cache line chunks, including bytes of a cache line. The cache line chunks may be chunks of one of the at least one cache line. Including the metadata in the FLIT avoids separately transmitting the at least one cache line and the metadata over the external link, which improves performance compared to generating separate transmissions. In some examples, the FLIT corresponds to a compute express link (CXL) protocol FLIT.