Cache Line Management Using de Bruijn Sequence Algorithm
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current cache memory systems face inefficiencies due to high latency and increased overhead when managing cache lines, particularly as the size of the cache memory and number of cache lines increase, leading to performance issues and the need for improved methods to determine available cache lines without relying on loops or unnecessary traversals.
Innovation Solution
A method utilizing a de Bruijn sequence algorithm to efficiently find available cache lines by determining the location of the least significant bit in a binary representation, allowing for systematic management of cache lines without loops, and using a lookup table to index stored messages for efficient retrieval and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of cache memory and number of cache lines increase, then the overall memory capacity is improved, but the overhead needed to search and fetch cache lines accumulates and leads to significant performance issues
Solution Approach 1:
The patent replaces the traditional loop-based mechanical search mechanism with a mathematical algorithm (de Bruijn sequence) that directly computes cache line availability. Instead of iteratively checking each cache line through loops, the system uses bit manipulation and precomputed sequences to determine available cache lines in constant time, substituting the mechanical traversal with a mathematical computation approach.
Solution Approach 2:
The patent precomputes de Bruijn sequences and stores them in lookup tables before runtime. These precomputed sequences enable the system to quickly determine cache line availability without performing complex calculations during cache operations. The preliminary preparation of these mathematical structures allows for efficient runtime performance regardless of cache size.
2Ease of operation
If current methods using loops or bitmap manipulation are used to determine cache line availability, then cache line management is achieved, but processor performance is degraded as the cache becomes full or size increases
Solution Approach 1:
The patent replaces loop-based iteration and bitmap manipulation with a mathematical algorithm using de Bruijn sequences. The system manipulates binary representations of cache line states through bit operations and lookup table indexing, eliminating the need for processor-intensive loops while maintaining the ability to determine cache line availability efficiently.
Solution Approach 2:
The patent uses bitmap representations where each bit corresponds to a cache line state (available or occupied). By manipulating these compact binary copies of cache line states through bit operations, the system can efficiently determine availability without accessing or iterating through actual cache line data, reducing processor overhead.
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
The invention relates to a method (100) of operating a cache module (400) comprising cache lines which are the smallest memory blocks of the cache module (400), wherein the method (100) comprises a step (110) of receiving an incoming message for storing, the step (110) of receiving comprising: determining (112) size of the message to in turn determine number of cache lines required for the message; finding (116) available cache lines required for the determined number of cache lines, wherein the step (116) of finding comprises: i. utilizing (116i) an algorithm using a de Bruijn sequence to find an available first cache line by determining the location of a least significant bit of value 1; ii. storing (116ii) the message or, if more than one cache line is required, part of the message in the first cache line in the cache module (400); iii. storing (116iii) the location of the first cache line in a lookup table (300) indexing details of the stored message; iv. repeating steps i to iii if more than one cache line is required for the message. The invention further relates to a computer program product and an electronic control unit comprising, among others, a processor configured to perform the method (100). The invention further relates to a vehicle control unit comprising a plurality of the electronic control units in electronic communication with each other by way of a data bus system.