Cache-Line Memory Compression for Lower DRAM Cost
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Solution Overview
Problem
Existing memory management techniques in servers face scalability issues due to high costs and performance bottlenecks, as increasing DRAM requirements significantly increase system costs and conventional compression techniques adversely affect performance.
Innovation Solution
Implementing inline physical memory compression using cache line-sized compression at the memory controller level, combining physical and cache memory compression techniques, which allows for reduced physical memory usage without impacting processing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more physical memory (DRAM) is added to increase memory capacity, then memory availability is improved, but system cost increases significantly
Solution Approach 1:
The patent combines physical memory compression with cache memory compression techniques, merging two separate compression approaches into a unified system that operates at the memory controller level, achieving both cost reduction and performance maintenance
Solution Approach 2:
The patent changes the compression block size parameter to match cache line size, optimizing the compression process to work efficiently with the memory hierarchy and achieve better compression ratios without performance penalty
2Ease of manufacture
If conventional compression techniques are used to reduce physical memory usage, then memory cost is reduced, but system performance deteriorates
Solution Approach 1:
The patent introduces a memory controller-level compression mechanism that acts as an intermediary between the CPU and physical memory, handling compression and decompression operations transparently without requiring CPU intervention, thus maintaining system performance
Solution Approach 2:
The patent performs compression on data before it is written to physical memory and decompression before data is read, preparing data in advance to avoid performance bottlenecks during actual memory operations
3Quantity of substance
If storage device compression is applied to reduce memory requirements, then physical memory usage is reduced, but system speed deteriorates
Solution Approach 1:
The patent replaces storage device-based compression with a memory controller-based compression system that operates in the memory hierarchy, substituting the mechanical compression process with a more efficient memory-level operation that does not bottleneck system speed
Data Source
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AI summary
A memory management system includes a physical memory (108) associated with a computing device and a memory manager (102). The memory manager is configured to manage a shared memory cache (106) as part of a compression of the physical memory using a cache compression algorithm, wherein a compression block size for the compression is a single cache line size. The physical memory includes a sector translation table (STT) region and a sector memory region. The memory manager uses a memory descriptor defined by an STT entry having a cache line map and a plurality of sector pointers to load cache from the physical memory to a level 3 Cache. The cache line map contains cache line metadata including a size of each cache line, a location of the cache line in one of the sectors pointed to by the STT entry, and a plurality of flags.