Cache Line Memory Erasure Information Storage
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Solution Overview
Problem
In memory modules, even small errors in a portion of a memory device can lead to the replacement of the entire device, resulting in large error-free portions being unused, as existing error correction methods lack sufficient granularity.
Innovation Solution
A memory controller is programmed to identify error-prone portions, ignore or correct data from these areas, and process data from error-free portions, using device numbers to determine which data to ignore or correct, thereby increasing the granularity of memory device replacement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction logic replaces entire memory devices when small errors occur, then reliability is improved, but productivity deteriorates due to unused error-free portions
Solution Approach 1:
The patent segments the memory system into cache lines, with each cache line containing data from multiple memory devices. Error correction is applied at the cache line level rather than the entire memory device level, allowing selective correction of only the portions containing errors while preserving error-free portions for continued use.
Solution Approach 2:
The patent applies error correction logic locally to specific cache lines and memory portions rather than globally to entire memory devices. This allows error-free portions to maintain their functional quality and continue being used, while only error-prone portions are corrected or replaced.
2Reliability
If spare memory devices are used to replace malfunctioning devices, then reliability is improved, but device complexity increases due to spare device management
Solution Approach 1:
The patent segments the replacement strategy to operate at the cache line level within existing memory devices rather than requiring replacement of entire devices. This eliminates the need for spare memory devices while maintaining reliability through localized error correction.
3Measurement precision
If entire memory devices are replaced for small errors, then measurement precision is improved for error detection, but loss of substance increases due to discarding error-free portions
Solution Approach 1:
The patent segments memory into cache lines and further into individual memory device contributions within each cache line. This fine-grained segmentation allows precise identification of error locations and selective correction or replacement of only the affected portions, preserving the majority of usable memory capacity.
Solution Approach 2:
The patent applies error detection and correction locally to specific cache lines and memory device contributions rather than treating entire memory devices uniformly. This allows error-free portions to continue being used at full capacity while only error-prone portions receive correction attention.
Data Source
AI summary
Example implementations relate to storing memory erasure information in memory devices on a memory module. In example implementations, a memory location associated with an error in a first cache line may be identified. The first cache line may include data read from the memory location, and the memory location may be in a first memory device of a plurality of memory devices on a memory module. A device number corresponding to the first memory device may be written to one of the plurality of memory devices. When the memory location is read for a second cache line, the device number corresponding to the first memory device may be retrieved. The second cache line may include the retrieved device number and data read from the memory location.