Cache Line Memory Ownership Detection for Self-Modifying Code
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Solution Overview
Problem
Modern processors face inefficiencies in detecting and preventing stale instructions caused by self-modifying code, particularly due to the slow process of transferring memory ownership between instruction and data caches, which leads to thrashing and reduced performance.
Innovation Solution
A processor system that determines memory ownership on a cache line basis using an ownership queue, which includes a fetch system, processing front end, and overwrite detector, to identify and handle self-modifying code by marking exceptions and flushing the processor to prevent execution of modified instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If memory ownership is transferred between instruction cache and data cache to detect self-modifying code, then detection accuracy is improved, but operation speed deteriorates due to slow transfer process
Solution Approach 1:
The patent applies preliminary action by pre-establishing ownership queues for each cache line in the instruction cache before self-modifying code execution occurs. These queues pre-store ownership information and wrap bits, so when a cache line is accessed, the ownership detection is already prepared and can be performed immediately without slow transfer operations. This transforms the post-detection approach into a pre-prepared state, eliminating the speed penalty.
Solution Approach 2:
The patent uses disposable wrap bits that are easily generated and discarded. Each cache line has an associated wrap bit that is computed once and then used for comparison. After the ownership detection, the wrap bit serves its purpose and is effectively discarded. This approach avoids the complexity and slowness of formal ownership transfer mechanisms while maintaining detection accuracy through simple bit comparison.
2Measurement precision
If ownership granularity is decreased to detect smaller code modifications, then detection precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory ownership detection into cache line-level units, with each cache line having its own ownership queue and wrap bit. This segmentation allows fine-grained detection at the cache line level (typically 64 bytes) without requiring complex page-level or word-level management. The segmentation is natural and hardware-friendly, as cache lines are already the fundamental unit of memory management in modern processors.
Solution Approach 2:
The patent changes the detection parameter from coarse-grained page ownership to fine-grained cache line ownership. By using the wrap bit as a simple binary parameter that flips when ownership changes, the system achieves high detection precision without complex data structures. The wrap bit transforms the continuous ownership state into a discrete, easily comparable parameter.
3Productivity
If prefetch operations are used to fill instruction cache, then execution speed is improved, but reliability deteriorates due to stale instructions
Solution Approach 1:
The patent implements feedback by continuously monitoring cache line ownership status through wrap bit comparison. When the processor executes instructions from the instruction cache, the wrap bit associated with each cache line is checked. If the wrap bit indicates an ownership change (self-modifying code), the system provides feedback to flush the instruction cache and invalidate stale instructions. This feedback mechanism maintains reliability without sacrificing prefetch-based execution speed.
Solution Approach 2:
The patent applies preliminary anti-action by proactively detecting ownership changes before they corrupt the instruction stream. The wrap bit is updated whenever a cache line is written to, creating a preliminary warning system. When the wrap bit mismatches during instruction execution, it signals that self-modifying code has occurred, and the processor can take corrective action (flushing the cache) before executing stale instructions. This prevents the reliability problem before it manifests.
Data Source
AI summary
A system and method of determining memory ownership on a cache line basis for detecting self-modifying code including code with looping instructions. An ownership queue includes multiple entries for determining memory ownership on a cache line basis. An ownership index and a wrap bit are determined for each cache line in the ownership queue, which are provided with each instruction derived from the same cache line. When an instruction is issued for execution, the ownership index provided with the instruction is used to access the corresponding entry in the ownership queue. If the instruction and entry wrap bits do not match, then an overwrite of the cache line is detected. The instruction is marked to invoke a first exception, which is performed when the instruction is ready to retire. The first exception flushes the processor, prevents the instruction from being retired, and re-fetches the instruction to continue processing.