Cache Line Owner Assignment for Direct Coherent LLC Transfer
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Solution Overview
Problem
Maintaining cache coherency in multiprocessor systems with an M×N mesh topology is inefficient when a cache line is evicted without an immediate owner, leading to potential data corruption and increased latency due to the need for temporary ownership assignment.
Innovation Solution
A method for direct data transfer with cache line owner assignment, where a coherent last level cache (LLC) transfers the cache line to the requesting cache coherency block (CCB) without intermediate ownership, using directory snoop filters (DSF) to manage ownership and invalidate sharers, reducing the need for temporary ownership and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If temporary ownership assignment is used when a cache line is evicted, then cache coherency can be maintained, but latency increases and system performance deteriorates
Solution Approach 1:
The patent extracts the temporary ownership assignment step from the cache line eviction process. When a cache line is evicted, the system directly transfers ownership to the requesting CCB without assigning temporary ownership to intermediate CCBs. This removes the time-consuming intermediate steps while maintaining coherency through direct ownership transfer and proper invalidation of sharers.
Solution Approach 2:
The patent performs preliminary actions by having the evicted cache line's home COA proactively transfer ownership to the requesting CCB before the requesting CCB needs to access the data. The home COA identifies the requesting CCB and initiates the ownership transfer in advance, eliminating waiting time and ensuring the requesting CCB can immediately proceed with its operations.
2Reliability
If intermediate ownership assignment is used during cache line transfer, then data corruption can be prevented, but the number of clock cycles increases
Solution Approach 1:
The patent removes the intermediate ownership assignment mechanism from the cache line transfer path. Instead of routing the cache line through multiple CCBs with temporary ownership, the system establishes a direct transfer path from the home COA to the requesting CCB. Data integrity is maintained through coherency protocols and invalidation signals rather than intermediate ownership.
Solution Approach 2:
The patent introduces the home COA as a mediator that directly coordinates the ownership transfer between the evicted cache line and the requesting CCB. This single intermediary replaces multiple intermediate CCB owners, reducing the number of handoff steps while ensuring data integrity through controlled transfer protocols and invalidation management.
3Reliability
If traditional cache coherency protocols are used, then all sharers can be notified of ownership changes, but the complexity of ownership management increases
Solution Approach 1:
The patent extracts the complex temporary ownership management logic from the traditional cache coherency protocol. By eliminating intermediate ownership assignments, the system removes the need for tracking multiple owners, managing ownership lifecycles, and coordinating complex transfer sequences. The coherency management is simplified to direct ownership transfer with invalidation notifications.
4Productivity
If direct data transfer without intermediate ownership is implemented, then performance improves, but the risk of data corruption increases
Solution Approach 1:
The home COA serves as a trusted intermediary that manages the direct transfer from evicted cache line to requesting CCB. It coordinates the ownership transfer, ensures proper invalidation of existing sharers, and maintains coherency protocols. This single intermediary provides the necessary safety checks without introducing the delays and complexities of multiple intermediate owners.
Data Source
AI summary
Techniques for data sharing are disclosed. A system-on-a-chip (SoC) is accessed. The SoC includes one or more cache coherency blocks (CCBs) and one or more coherency ordering agents (COAs). Each COA includes a directory snoop filter (DSF). Each CCB is communicatively coupled to each COA by a network-on-a-chip (NOC) interface. A CCB requests a cache line associated with a memory address. The CCB is not a sharer of the cache line. A directory snoop filter (DSF) within a COA is read. The reading reveals one or more CCB sharers of the cache line and indicates there is no CCB owner. The COA includes a coherent last level cache (LLC) that contains a valid copy of the cache line. The COA assigns ownership of the cache line to the CCB. The assigning is recorded in the DSF. The cache line is forwarded by the coherent LLC to the CCB.