Cache Line Page Attribute Storage for TLB Lookup Reduction
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Solution Overview
Problem
In processing systems with paged virtual memory, the large size of page tables and the need for memory accesses during address translation lead to time-consuming and power-consuming TLB lookups, and storing memory attributes in TLBs increases the number of bits to be accessed, slowing down lookups and consuming more power.
Innovation Solution
A processing system with a memory cache that stores both address and data lines, allowing page attributes to be retrieved using a virtual address without accessing the TLB, thereby reducing the need for TLB lookups and storing memory attributes as extra bits in cache lines instead of TLBs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory attributes are stored in the TLB, then attribute access is enabled, but the number of bits to be accessed increases, slowing down lookups and consuming more power
Solution Approach 1:
The patent segments the attribute storage function by creating a separate attribute cache structure that is independent from the TLB. This allows the TLB to focus solely on address translation while attributes are cached separately, enabling parallel access and eliminating the need to access additional bits in the TLB during address translation operations.
Solution Approach 2:
The patent introduces an intermediary attribute cache structure that mediates between the TLB and the attribute storage. This intermediary component receives attribute information from the TLB and provides it to the attribute access logic, allowing attribute retrieval without requiring the TLB itself to contain and access attribute bits during the translation process.
2Reliability
If memory attributes are stored in the TLB, then attribute access is enabled, but power consumption increases due to accessing more bits
Solution Approach 1:
The patent segments the attribute storage function by creating a separate attribute cache structure that is independent from the TLB. This allows the TLB to focus solely on address translation while attributes are cached separately, enabling parallel access and eliminating the need to access additional bits in the TLB during address translation operations.
Solution Approach 2:
The patent introduces an intermediary attribute cache structure that mediates between the TLB and the attribute storage. This intermediary component receives attribute information from the TLB and provides it to the attribute access logic, allowing attribute retrieval without requiring the TLB itself to contain and access attribute bits during the translation process.
3Reliability
If page tables are stored in system memory, then complete address translation information is available, but memory accesses are required which are time-consuming
Solution Approach 1:
The patent extracts frequently accessed attribute information from the page tables in system memory and stores it in a separate attribute cache structure. This extraction allows the system to retrieve attributes without requiring full page table walks in system memory, significantly reducing memory access time while maintaining translation accuracy through the TLB and attribute cache.
Solution Approach 2:
The patent performs preliminary action by pre-fetching and caching attribute information in the attribute cache structure before it is needed for attribute access. This preliminary caching of attributes alongside the TLB mechanism ensures that when address translation occurs, the attributes are already available in fast storage, eliminating the need for time-consuming memory accesses during the translation process.
Data Source
AI summary
A processing system may include a memory configured to store data in a plurality of pages, a TLB, and a memory cache including a plurality of cache lines. Each page in the memory may include a plurality of lines of memory. The memory cache may permit, when a virtual address is presented to the cache, a matching cache line to be identified from the plurality of cache lines, the matching cache line having a matching address that matches the virtual address. The memory cache may be configured to permit one or more page attributes of a page located at the matching address to be retrieved from the memory cache and not from the TLB, by further storing in each one of the cache lines a page attribute of the line of data stored in the cache line.