Cache-Line Memory Compression with Sector Translation Tracking
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Solution Overview
Problem
Current memory management techniques in server applications face challenges in scalability due to high costs associated with increasing dynamic RAM (DRAM) and existing compression methods that adversely affect system performance.
Innovation Solution
Implementing a computerized method for tracking compressed memory using a sector translation table with a cache line map and sector pointers, allowing for inline physical memory compression at the cache line size, which reduces the need for physical memory without impacting processing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the amount of physical memory (DRAM) is increased to reduce bottlenecks and improve processor performance, then system performance is improved, but system cost increases significantly
Solution Approach 1:
The patent changes the state of physical memory from uncompressed to compressed form, allowing more logical memory to be stored in the same physical space. By applying compression algorithms to memory data, the system effectively increases the amount of usable memory without adding physical DRAM modules, thus improving processor performance while avoiding increased hardware costs.
Solution Approach 2:
The patent creates a virtual memory space that is larger than the physical memory by using compression. The compressed memory acts as a copy or representation of the physical memory, allowing the system to access more data than would physically fit in DRAM, thereby reducing bottlenecks and improving overall system performance without additional hardware investment.
2Quantity of substance
If memory compression techniques are applied to reduce physical memory requirements, then system cost is reduced, but system performance is adversely affected
Solution Approach 1:
The patent extracts the compression and decompression operations from the critical memory access path. By implementing compression at the memory controller level and using pre-computed compression indicators, the system removes the performance penalty typically associated with on-the-fly compression, allowing physical memory reduction without sacrificing system performance.
Solution Approach 2:
The patent performs compression indicators calculation and compression status determination in advance, before actual memory access occurs. By pre-processing memory data and determining which blocks are compressible, the system eliminates runtime compression overhead during critical access paths, thereby maintaining high performance while still achieving physical memory reduction through compression.
3Quantity of substance
If compression is performed on the storage device to reduce memory requirements, then physical memory usage is reduced, but system speed is adversely affected
Solution Approach 1:
The patent introduces a memory controller-level compression layer as an intermediary between the physical DRAM and the processor. This intermediary handles compression and decompression operations transparently, allowing the processor to access compressed memory at speeds approaching uncompressed memory access, thereby reducing physical memory usage without significantly impacting system speed.
Data Source
AI summary
A memory management system includes a physical memory associated with a computing device and a memory manager. The memory manager is configured to manage a shared memory cache as part of a compression of the physical memory using a cache compression algorithm, wherein a compression block size for the compression is a single cache line size. The physical memory includes a sector translation table (STT) region and a sector memory region. The memory manager uses a memory descriptor defined by an STT entry having a cache line map and a plurality of sector pointers to load cache from the physical memory to a level 3 Cache. The cache line map contains cache line metadata including a size of each cache line, a location of the cache line in one of the sectors pointed to by the STT entry, and a plurality of flags.