Cache Line Assembly for Sparse Noncontiguous Data Access
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Solution Overview
Problem
Existing cache mechanisms require modification or the addition of jump wires to handle sparse data access, leading to increased complexity and chip manufacturing costs, and affect data loading performance in scenarios involving non-sparse and noncontiguous addresses.
Innovation Solution
A data access method that combines data from multiple source storage addresses into a cache line length, allowing efficient data loading without modifying the cache mechanism or adding jump wires, by reading and combining data at a granularity less than the cache line length and using existing bus transmission protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the sub cache line technique is used for sparse data access, then data access efficiency for sparse addresses is improved, but chip manufacturing costs increase and existing cache mechanism requires modification
Solution Approach 1:
The patent combines multiple small data reads from different addresses into a single cache line-sized read operation. The memory controller collects data from multiple source addresses, pads it to fill a complete cache line, and transfers it in one operation, merging multiple small transactions into one efficient transfer that utilizes the full cache line bandwidth.
Solution Approach 2:
The patent makes the existing cache mechanism and memory interface universal by designing a solution that works for both sparse and non-sparse data access scenarios without requiring separate hardware paths. The same cache line transfer mechanism is used for all data types, eliminating the need for specialized sub-cache line infrastructure.
2Productivity
If the sub cache line technique is used for sparse data access, then data access granularity is improved, but device complexity increases due to new memory access channel and protocol
Solution Approach 1:
The patent segments the data transfer process into two phases: data collection phase where small data pieces are gathered from multiple addresses, and data transfer phase where the consolidated cache line is transferred in one operation. This segmentation allows fine-grained data collection while maintaining coarse-grained efficient transfer through the existing interface.
Solution Approach 2:
The memory controller acts as an intermediary that receives fine-grained data read requests for multiple addresses, consolidates them into a cache line-sized data structure, and then presents it as a single standard cache line transfer to the processing subsystem. This intermediary function enables fine-grained access semantics while using coarse-grained transfer mechanics.
3Adaptability or versatility
If the sparse-data access buffer determines access channel first, then sparse data access is enabled, but non-sparse data access complexity increases and data loading performance is affected
Solution Approach 1:
Instead of determining the access channel first and then fetching data, the patent inverts the approach by directly issuing standard cache line-sized read requests for multiple addresses simultaneously, collecting the results, and then consolidating them. This eliminates the need for preliminary channel determination logic.
Solution Approach 2:
The system uses the existing memory interface and cache mechanisms to serve itself without requiring separate determination logic or control paths. The same infrastructure that handles regular cache line transfers is used for sparse data access, with the memory controller automatically handling the consolidation process.
Data Source
AI summary
A data access method includes: receiving a data request, where the data request indicates a plurality of source storage addresses and a target data type; reading, from a memory based on the data request, a first memory block indicated by each of the plurality of source storage addresses, where a length of the first memory block is a granularity for accessing the memory; extracting data of each source storage address from the first memory block indicated by each source storage address; combining data of all the source storage addresses based on a length of a cache line to obtain a second memory block; and sending the second memory block to a processing subsystem, for the processing subsystem to cache the second memory block.