Cache Line Split Prefetching for Zero-Latency Instruction Fetch
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Solution Overview
Problem
Conventional prefetch techniques in digital data processors consume resources and are given lower priority, leading to inefficiencies in instruction fetching from caches.
Innovation Solution
A dual cache system with a level one instruction cache and a level two cache, where the level two cache prefetches the lower half of a cache line upon a miss in the level one cache, reducing resource consumption and enhancing prefetch efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional prefetch techniques are used, then instructions can be fetched ahead of time, but resource consumption increases and prefetch priority decreases
Solution Approach 1:
The cache system is segmented into two hierarchical levels: a first level cache and a second level cache. The second level cache is further divided into an upper half and a lower half, each handling different portions of the instruction fetch process. This segmentation allows the system to perform prefetching operations in the second level cache without consuming resources in the first level cache, thereby reducing overall resource consumption while maintaining prefetch functionality.
Solution Approach 2:
The second level cache acts as an intermediary between the first level cache and the external memory. When the first level cache misses an instruction fetch, it requests the instruction from the second level cache, which may perform prefetching operations. This intermediary structure allows prefetching to occur at a lower resource cost, as the second level cache handles the prefetching rather than the first level cache.
2Productivity
If prefetch requests are processed with high priority, then instruction availability improves, but resource allocation to other operations decreases
Solution Approach 1:
The cache system segments prefetching operations from demand fetch operations by separating them into different hierarchical levels. The second level cache handles prefetching operations independently, allowing the first level cache to focus on rapid demand fetch operations. This segmentation enables the system to maintain high instruction fetch speed without allocating excessive resources to prefetching, as prefetching occurs at a lower level with reduced resource requirements.
3Reliability
If the second level cache supplies the entire cache line at once, then data availability increases, but prefetch efficiency decreases due to resource consumption
Solution Approach 1:
The second level cache line is segmented into an upper half and a lower half. When a prefetch request is made, the system can supply only the necessary portion (the lower half) rather than the entire cache line. This segmentation allows the system to maintain data availability for the required instructions while reducing the amount of data transferred, thereby improving prefetch efficiency and reducing resource consumption.
Solution Approach 2:
Instead of always supplying the entire cache line from the second level cache, the system performs partial action by supplying only the lower half when prefetching is required. This partial action approach reduces the overhead of data transfer and processing, improving prefetch efficiency while still providing sufficient data availability for the instructions being fetched.
Data Source
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AI summary
Described examples relate to a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. The cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. The central processing unit core requests additional program instructions when needed via a request address. Upon a miss (2302) in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache (2309). On a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache (2310). This cache technique thus prefetches the lower half level two cache line employing fewer resources than an ordinary prefetch.