Cache Line Timer Write-Back for Bitflip Reliability

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Solution Overview

Problem

The reliability of cache lines in a modified state is compromised due to prolonged storage, which increases the probability of bitflips leading to data errors.

Innovation Solution

Implementing a timer-based mechanism to monitor cache lines in a modified state, writing them back to a next-level memory when the timer expires, ensuring data backup and reducing the duration in the modified state to prevent bitflips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the cache line is stored in the memory for a long time in modified state, then the data can be retained in the cache, but the probability of bitflip increases and reliability decreases

Engineering Contradiction:

Improvereliability of cache lineVSAvoidstorage duration of cache line

Core Design Contradiction:

ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent applies preliminary action by proactively writing the cache line back to memory before a bitflip can occur. The system monitors the modified state duration and initiates the write-back operation when the timer expires, preventing data corruption rather than detecting and correcting it after the fact.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback through a timer mechanism that continuously monitors how long a cache line has remained in the modified state. When the timer expires, it triggers a write-back operation, creating a closed-loop control system that dynamically manages cache line reliability based on storage duration.

Inventive Principle:

Principle #23Feedback

2Reliability

If the cache line is written back frequently to next-level memory, then reliability is improved, but write operations increase and productivity decreases

Engineering Contradiction:

Improvereliability of cache lineVSAvoiddata processing efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies dynamics by making the write-back operation conditional rather than static or periodic. The cache line is written back only when it transitions to modified state and the timer expires, adapting the write-back frequency to actual usage patterns and minimizing unnecessary write operations.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of write-back timing from fixed periodic intervals to event-driven timing based on cache line state transitions. The timer is started only when the cache line enters modified state, and the write-back occurs only when the timer expires, optimizing the balance between reliability and productivity.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20250363054A1Data Processing Method, Apparatus, Chip, and Computer Device

Publication Date: 2025.11.27 HUAWEI TECH CO LTD

AI summary

A data processing method includes starting, based on a state of a cache line in a memory changing from a non-modified state to a modified state, a timer of the cache line; and writing the cache line back to a next-level memory when the timer of the cache line expires such that the cache line does not remain in the modified state for a long time. When the timer of the cache line expires, the cache line is written back to the next-level memory, and data of the cache line is backed up.