Hierarchical Cache Line Tracker for Virtualized Memory

The patent divides the memory tracking granularity from page-level to cache line-level by implementing a cache line tracker that monitors individual cache lines. The tracker uses a hierarchical bitmap data structure where each bit represents the dirty state of a specific cache line, enabling selective tracking of only modified cache lines rather than entire pages. This segmentation allows the system to write back only the necessary cache lines to persistent storage, reducing memory and bandwidth requirements while maintaining implementation feasibility through the structured bitmap approach.

The patent introduces a cache line tracker as an intermediary component that sits between the processing hardware and persistent storage. This tracker includes monitoring hardware that intercepts cache coherence events (such as write requests) on the coherence interconnect, determines which cache lines are modified, and updates the hierarchical bitmap accordingly. By placing this intermediary layer, the system achieves fine-grained cache line tracking without requiring complex modifications to the existing memory hierarchy or storage subsystem, as the tracker handles all the complexity of monitoring and tracking internally.

The patent applies partial action by implementing selective write-back of only the dirty cache lines identified in the hierarchical bitmap, rather than writing back entire pages. The monitoring hardware tracks which specific cache lines have been modified by detecting cache coherence events, and the write-back operation is triggered only for those marked as dirty in the bitmap. This partial approach maintains data consistency for modified cache lines while avoiding unnecessary data transfer of clean cache lines, thereby significantly improving write-back efficiency without compromising reliability.