Cache Line Selection Using Unused Line Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The use of a second FIFO between main memory and cache to avoid write-before-read hazards consumes area and power, and may overwrite data needed for subsequent requests, which is problematic in mobile devices where space and battery life are concerns.
Innovation Solution
Identifying and selecting unused cache lines during a test interval to write new data, using bits or flags associated with each cache line to determine if they have been referenced, thus avoiding the need for a second FIFO.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a second FIFO is used between main memory and cache to avoid write-before-read hazards, then data integrity is improved, but area and power consumption increase
Solution Approach 1:
The patent extracts the delay function from a physical second FIFO buffer and implements it using the existing first FIFO buffer by tracking packet ages. Instead of adding a separate buffering component, the system uses metadata (age counters) in the existing buffer to simulate the timing delay that would otherwise require dedicated hardware, thereby eliminating the area overhead while maintaining data integrity
Solution Approach 2:
The patent creates a virtual representation of the second FIFO's delay function through age counters that track packet timestamps. Rather than physically duplicating the FIFO structure, the system copies the timing behavior through software-managed metadata, allowing the same physical buffer to serve multiple logical functions without requiring additional hardware area
2Reliability
If a second FIFO is used between main memory and cache to avoid write-before-read hazards, then data integrity is improved, but power consumption increases
Solution Approach 1:
The patent merges the delay function with the existing first FIFO buffer by using age counters to track packet timestamps. Instead of operating a separate second FIFO that would consume additional power, the system combines multiple functions (buffering, timing delay, and hazard detection) into a single buffer structure with enhanced metadata, reducing overall power consumption while maintaining reliability
Solution Approach 2:
The system uses the existing FIFO infrastructure to serve the delay function that would otherwise require a second FIFO. By having the first FIFO buffer track its own packet ages and use this information for hazard detection, the system eliminates the need for additional powered components, allowing the existing structure to self-serve multiple purposes
3Productivity
If new data is written to cache immediately after cache miss, then cache utilization is improved, but write-before-read hazards occur
Solution Approach 1:
The patent implements a feedback mechanism where age counters track the timestamp of packets in the FIFO buffer. Before writing new data to cache, the system queries these age counters to determine whether preceding packets have been fully processed. This feedback loop allows the system to dynamically control cache write timing, ensuring data integrity while maximizing cache utilization by writing as soon as safety is confirmed
Solution Approach 2:
The system performs preliminary checking of packet ages before allowing cache writes. By pre-tracking the timestamps of all packets in the FIFO and continuously monitoring their age, the system is already prepared with the information needed to safely proceed with cache writes, eliminating the need for conservative delays while preventing write-before-read hazards
Data Source
AI summary
In the event of a cache miss, data is written from main memory to the cache. To select a cache line to write the data to, cache lines in the cache that are not referenced during a certain interval are identified. One of the identified cache lines is selected and the data can be written to that cache line.