Cache Linefill Delegation for Slot Occupancy Bottlenecks
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Solution Overview
Problem
The finite number of linefill slots in cache levels can create a bottleneck, leading to stalling of new requests and delays in data processing due to high cache miss rates, particularly when new linefill requests occur more frequently than they can be accommodated by the available slots.
Innovation Solution
Implementing a slot allocation procedure in level N cache levels that modifies slot allocation based on occupancy criteria, allowing linefill delegation to level M cache levels, which includes selecting a victim slot for non-demand requests and utilizing prefetch pipelines to handle speculative requests, thereby reducing the pressure on level N cache slots.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of linefill slots is increased to accommodate more pending requests, then the cache level can handle more simultaneous linefill requests, but the device complexity and resource consumption increase
Solution Approach 1:
The patent extracts the linefill processing function from the level N cache level and relocates it to the level M cache level. By taking out the linefill slots and their associated processing logic from the upper cache level, the system reduces the complexity of level N while maintaining the ability to handle multiple simultaneous linefill requests through the level M cache's linefill slots.
2Reliability
If the slot allocation procedure is modified to prioritize demand requests, then the cache performance for critical requests improves, but the handling of speculative requests may be delayed
Solution Approach 1:
The patent segments the linefill request handling into two distinct paths: demand requests are handled through the prioritized slot allocation procedure at level N, while speculative requests are routed through prefetch pipelines to level M. This segmentation allows different quality-of-service treatments for different request types without mutual interference, maintaining reliability for demand requests while managing speculative requests through alternative mechanisms.
3Productivity
If linefill delegation to level M cache is implemented, then the bottleneck at level N is reduced, but the system complexity increases due to additional delegation logic
Solution Approach 1:
The patent implements feedback mechanisms where the level N cache monitors its linefill slot occupancy and the performance characteristics of different request types. Based on this feedback, the slot allocation procedure dynamically adjusts priorities and delegation decisions. The system uses occupancy criteria and request type information to make intelligent delegation choices, optimizing throughput while managing complexity through adaptive control rather than static rigid rules.
Data Source
AI summary
Apparatuses, methods, systems, and chip-containing products are disclosed, which relate to an arrangement comprising a level N cache level and a level M cache level, where M is greater than N. The level N cache level comprises a plurality of linefill slots and performs a slot allocation procedure in response to a lookup miss in dependence on a linefill slot occupancy criterion. The slot allocation procedure comprises allocation of an available slot of the plurality of slots to a pending linefill request generated in response to the lookup miss. The level N cache level effects a modification of the slot allocation procedure in dependence on the linefill slot occupancy criterion and is responsive to the linefill slot occupancy criterion being fulfilled to cause a linefill delegation action to be instructed to the level M cache level.