Cache Logic Linefill Eviction and Invalidation Timing
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Solution Overview
Problem
In data processing apparatuses, the performance is impacted by the significant time gap between evicting a cache line's content and marking it as invalid, leading to cache misses and inefficiencies when subsequent access requests are made to the evicted content before the new content is available, causing delays and additional linefill operations.
Innovation Solution
The cache logic performs a linefill process by evicting the current content of a selected cache line while keeping it valid, allowing read access requests to continue hitting in the cache and preventing write access requests until the new content is available, thereby delaying the invalidation of the cache line until the new content is stored.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the cache line is marked as invalid immediately after eviction, then the cache structure is simplified and write access is prevented, but read access requests to the evicted content cannot be served and must wait for linefill operations
Solution Approach 1:
The patent applies preliminary action by keeping the evicted cache line content valid temporarily instead of immediately invalidating it. This allows read access requests to be served from the still-valid cache line content before the linefill operation completes, avoiding cache misses and improving access efficiency. The invalidation is delayed until the new content is ready to be written, at which point the old content is no longer needed.
2Productivity
If the current content of the evicted cache line is kept valid during eviction, then read access requests can continue to hit in the cache, but write access requests may cause non-atomic read and write hazards
Solution Approach 1:
The patent applies local quality by differentiating the treatment of read and write access requests to the evicted cache line. Read requests are allowed to access the still-valid content, while write requests are blocked or handled specially to prevent non-atomic operations. This selective access control maintains data consistency for writes while allowing reads to benefit from the valid cache content.
Data Source
AI summary
Cache logic is provided for use in a data processing apparatus, the cache logic having a cache storage comprising a plurality of cache lines for storing data values. Control logic is arranged, in response to an access request issued by a device of the data processing apparatus identifying a memory address of the data value to be accessed, to cause a lookup operation to be performed to determine whether the data value for that memory address is stored within the cache storage. The control logic is further operable if the data value is not stored in the cache storage to perform a linefill process, the linefill process comprising performing an eviction to evict to memory of the data processing apparatus current content of a selected cache line, keeping the current content valid in the selected cache line whilst the eviction is taking place, and storing from the memory into the selected cache line new content including the data value the subject of the access request. Whilst the eviction is taking place, the control logic allows the current content of the selected cache line to be accessed by subsequent read access requests seeking to read a data value within that current content, but prevents the current content of the selected cache line being accessed by subsequent write access requests seeking to write to a data value within that current content.