Cache Load Scheduler Resolves Fill-Load Port Conflicts

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Solution Overview

Problem

Cache access conflicts between load and fill requests occur due to limited read/write ports in caches, leading to delays or denials of load requests when fill requests overwhelm the available ports, especially in systems with small cache sizes and high access frequencies.

Innovation Solution

A system and method that utilize a load scheduler in the cache to derive address and timing information from incoming fill signals, allowing it to schedule load requests to avoid conflicts by rearranging the order of load requests or delaying them to prevent port overloads, thereby ensuring efficient data retrieval from memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the cache size is kept small to be cost-effective, then the cache can be implemented efficiently, but cache access conflicts occur more frequently when multiple load and fill requests compete for limited ports

Engineering Contradiction:
Improvecache sizeVSAvoidcache access conflict frequency
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The load scheduler circuit predicts future fill requests before they actually occur by analyzing incoming fill signals and deriving timing information. This preliminary prediction allows the system to proactively schedule load requests to avoid future conflicts, rather than reactively handling conflicts after they occur. The scheduler uses the predicted timing to rearrange or delay load requests in advance, preventing port overloads before they happen.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If more read/write ports are added to the cache to handle concurrent requests, then cache access conflict frequency is reduced, but the cache complexity and cost increase

Engineering Contradiction:
Improvecache access conflict frequencyVSAvoidcache port structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The load scheduler circuit acts as an intermediary between load requests and the cache ports. Instead of adding more physical ports to handle concurrent requests, the scheduler mediates access by intelligently sequencing and timing load requests to avoid conflicts with fill operations. This software-like scheduling approach replaces hardware expansion, managing port utilization efficiently without increasing physical complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If load requests are processed immediately without scheduling, then the system operates simply, but load requests may be delayed or denied when fill requests overwhelm the ports

Engineering Contradiction:
Improveload request throughputVSAvoidload request completion rate
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The load scheduler circuit performs preliminary scheduling of load requests by predicting when fill requests will occur and arranging load requests accordingly. This preliminary organization ensures that load requests are staged to be processed at optimal times when ports are available, maximizing throughput while preventing denials. The scheduler maintains a queue of pending load requests and releases them in an optimized sequence rather than immediately.

Inventive Principle:
Principle #10Preliminary action

4Device complexity

If the cache uses a simple direct-mapped structure, then the cache is easier to implement, but cache access conflicts increase when multiple requests target the same cache line

Engineering Contradiction:
Improvecache structureVSAvoidcache access conflict frequency
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The load scheduler circuit implements feedback by monitoring incoming fill signals and using the derived timing information to adjust its scheduling decisions. The scheduler continuously adapts its load request timing based on observed fill patterns, creating a closed-loop system that learns and optimizes its scheduling strategy. This feedback mechanism allows the simple cache structure to operate efficiently by dynamically avoiding conflicts based on real-time information.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10649900B2Method to avoid cache access conflict between load and fill
Publication Date: 2020.05.12 SAMSUNG ELECTRONICS CO LTD
  • US10649900B2 patent drawing
  • US10649900B2 patent drawing
  • US10649900B2 patent drawing

AI summary

According to one general aspect, an apparatus may include a first cache configured to store data. The apparatus may include a second cache configured to, in response to a fill request, supply the first cache with data, and an incoming fill signal. The apparatus may also include an execution circuit configured to, via a load request, retrieve data from the first cache. The first cache may be configured to: derive, from the incoming fill signal, address and timing information associated with the fill request, and based, at least partially, upon the address and timing information, schedule the load request to attempt to avoid a load-fill conflict.