Cache Location Buffer for Energy-Efficient Data Access

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Solution Overview

Problem

Current cache hierarchies face significant energy consumption and overhead due to numerous associative lookups required to determine cache line locations, which complicates efficient data access and increases latency.

Innovation Solution

Implementing a cache location buffer (CLB) that stores location information for cachelines, allowing direct access to cache levels without the need for additional associative lookups by using address tags, thereby reducing energy consumption and improving access times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If conventional cache hierarchies use associative lookups to determine cache line locations, then cache access can be performed, but energy consumption increases and access time is extended

Engineering Contradiction:
Improvecache access energyVSAvoidcache access time
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The cache system is segmented into two distinct parts: a tag-less cache structure for rapid data access and a separate cache location buffer (CLB) that stores pre-computed location information. This segmentation allows the cache to avoid full associative lookups by using the CLB's direct addressing mechanism, thereby reducing both energy consumption and access time while maintaining correctness through the tag verification path.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The cache location buffer (CLB) acts as an intermediary structure between the cache controller and the tag-less cache. It stores pre-computed location information (way and set indices) that mediates the access process, allowing the system to bypass the energy-intensive and time-consuming associative tag comparison while still enabling correct cache line identification through direct addressing.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If tag comparisons are performed in cache hierarchies, then cache line locations can be determined, but numerous associative lookups increase overhead and reduce efficiency

Engineering Contradiction:
Improvecache access efficiencyVSAvoidcache structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the tag comparison functionality from the traditional unified cache structure and separates it into a dedicated cache location buffer (CLB). The CLB stores pre-computed location information that is extracted from the original address, allowing the main cache access path to operate without performing associative tag comparisons, thus improving productivity while managing complexity through functional separation.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system performs preliminary action by pre-computing and storing location information (way and set indices) in the cache location buffer before actual cache access occurs. This preliminary computation of addresses and storage of location metadata in the CLB eliminates the need for real-time tag comparisons during cache access, significantly improving access efficiency while the complexity is handled during the setup phase rather than during critical access operations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10409725B2Management of shared pipeline resource usage based on level information
Publication Date: 2019.09.10 SAMSUNG ELECTRONICS CO LTD
  • US10409725B2 patent drawing
  • US10409725B2 patent drawing
  • US10409725B2 patent drawing

AI summary

The execution or processing of an application can be adapted or modified based on a level of a cache in which a requested data block resides, by extracting level information from a cache hierarchy. When a request for a data block is made by a core to a cache memory system, the cache memory system extracts a level of a cache memory in which the data block resides from information stored in the cache memory system. The core is informed of the level of the cache memory in which the data block resides, and uses this information to adapt its processing of the application.