Cache Location Buffer Eliminates Tag Lookups
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Solution Overview
Problem
Current cache hierarchies require numerous associative lookups and store additional address tags, leading to high energy consumption and overhead in determining cache line locations, which is inefficient and costly in terms of both energy and memory capacity.
Innovation Solution
Implementing a cache location buffer (CLB) that stores cache location information and address tags, allowing direct access to cache lines without additional associative lookups by updating location information when cache lines are moved within the hierarchy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If address tags are stored in each cache level to enable precise cache line location identification, then cache hit/miss determination accuracy is improved, but memory capacity is consumed and energy usage increases
Solution Approach 1:
The patent extracts the tag storage function from individual cache levels and consolidates it into a separate tag cache structure. This allows the main cache to store only data without redundant tags, reducing memory capacity consumption while maintaining the ability to identify cache line locations through the dedicated tag cache.
Solution Approach 2:
The tag cache serves multiple functions: it stores tags for multiple cache levels, enables hit/miss determination, and tracks cache line locations across the hierarchy. This multi-functional approach reduces the total memory capacity needed compared to having separate tag storage at each cache level.
2Measurement precision
If address tags are stored and compared at each cache level to determine cache line locations, then cache hit/miss determination accuracy is improved, but energy consumption increases
Solution Approach 1:
The patent extracts the tag comparison operation from each cache level access and consolidates it into a centralized tag cache lookup. This reduces the total number of comparison operations needed, as a single tag cache lookup can determine the location of a cache line across multiple cache levels, thereby reducing energy consumption.
Solution Approach 2:
The tag cache pre-stores tag information for multiple cache levels, enabling preliminary identification of cache line locations before actual data access. This preliminary action avoids the need for multiple sequential tag comparisons at different cache levels, reducing the energy required for cache hit/miss determination.
3Measurement precision
If multiple associative lookups are performed to determine cache line locations across cache levels, then cache hit/miss determination accuracy is improved, but access time increases
Solution Approach 1:
The patent merges the tag storage and lookup functionality across multiple cache levels into a single unified tag cache structure. This consolidation allows a single associative lookup to determine cache line locations across the entire hierarchy, eliminating the need for multiple sequential lookups and reducing access time while maintaining identification accuracy.
Solution Approach 2:
The tag cache provides universal tag lookup capability for multiple cache levels simultaneously. A single lookup in the tag cache can identify cache line locations at any level in the hierarchy, replacing multiple level-specific lookups and thereby reducing the total access time required for cache hit/miss determination.
Data Source
AI summary
Methods and systems which, for example, reduce energy usage in cache memories are described. Cache location information regarding the location of cachelines which are stored in a tracked portion of a memory hierarchy is stored in a cache location table. Address tags are stored with corresponding location information in the cache location table to associate the address tag with the cacheline and its cache location information. When a cacheline is moved to a new location in the memory hierarchy, the cache location table is updated so that the cache location information indicates where the cacheline is located within the memory hierarchy.