Cache Locking for Register Data Eviction Control
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Solution Overview
Problem
In unified memory architectures, register data evictions from cache levels can lead to performance issues when the data is accessed again after eviction, particularly in graphics processing units (GPUs), due to complex tracking of register usage which increases circuit area and power consumption.
Innovation Solution
Implementing lock frames with lock indicators per architectural register or SIMD group, preventing eviction of cache lines storing register data by setting lock bits, and bulk unlocking when certain conditions are met, such as a threshold number of locks or channel stalling, to preserve register data closer to execution pipelines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If register data is memory-backed in cache levels without precise tracking, then power consumption and circuit area are reduced, but register data may be evicted from cache leading to performance degradation
Solution Approach 1:
The patent applies partial tracking by using lock indicators for only some registers (those that are locked) rather than tracking all register data precisely. This partial action approach reduces the tracking overhead and power consumption while still protecting the most critical register data from eviction, achieving a balance between power efficiency and performance.
Solution Approach 2:
The patent implements local quality by applying different cache management policies to different registers. Locked registers receive protection from eviction through lock indicators, while non-locked registers follow standard cache eviction policies. This localized differentiation allows the system to focus resources on protecting only the registers that require preservation, reducing overall power consumption while maintaining performance for critical data.
2Reliability
If precise tracking of register usage is implemented, then register data eviction is prevented, but power consumption and circuit area increase
Solution Approach 1:
The system performs partial tracking by monitoring and locking only the necessary register data rather than all register data. The lock indicator mechanism selectively protects only those registers that need preservation, avoiding the power consumption and circuit area overhead of comprehensive tracking while ensuring reliability for critical register data.
Solution Approach 2:
The patent extracts the essential function of register tracking by removing the need for complex, full-scale tracking mechanisms. Instead, it extracts only the critical protection function through simple lock indicators that can be set and cleared, eliminating unnecessary tracking overhead while maintaining the core reliability function for preserved register data.
3Reliability
If lock indicators are maintained for all registers, then register data is preserved in cache, but circuit area and complexity increase
Solution Approach 1:
The patent merges the lock indicator storage with existing cache structures rather than implementing separate tracking hardware. The lock indicators are integrated into the cache tag or metadata structures, combining the protection function with existing cache management infrastructure. This merging approach preserves register data in cache while avoiding the additional circuit area and complexity that would result from separate tracking mechanisms.
Solution Approach 2:
The lock indicator mechanism serves multiple functions: it protects register data from eviction, provides a simple interface for software control, and integrates with existing cache management. This multi-functionality reduces the need for separate dedicated tracking circuitry, thereby reducing overall device complexity and circuit area while maintaining reliable cache data preservation.
Data Source
AI summary
Techniques are disclosed relating to eviction control for cache lines that store register data. In some embodiments, memory hierarchy circuitry is configured to provide memory backing for register operand data in one or more cache circuits. Lock circuitry may control a first set of lock indicators for a set of registers for a first thread, including to assert one or more lock indicators for registers that are indicated, by decode circuitry, as being utilized by decoded instructions of the first thread. The lock circuitry may preserve register operand data in the one or more cache circuits, including to prevent eviction of a given cache line from a cache circuit based on an asserted lock indicator. The lock circuitry may clear the first set of lock indicators in response to a reset event. Disclosed techniques may advantageously retain relevant register information in the cache with limited control circuit area.