Cache Locking via Translation Table Address Extraction
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Solution Overview
Problem
Current cache locking mechanisms require significant hardware overhead due to the need to maintain both virtual and physical addresses, leading to increased space requirements on microprocessors and decreased performance.
Innovation Solution
Implementing a translation table to store address and locking information, allowing the cache to lock data based on this information and override the replacement mechanism, thereby reducing the need for explicit address storage and hardware usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If both virtual address and physical address are maintained in load and store queues to implement cache locking, then cache locking functionality is achieved, but hardware overhead and area occupation increase significantly
Solution Approach 1:
The patent extracts the address storage function from the load and store queues by implementing a dedicated cache locking mechanism that stores only the address to be locked in a separate register file, eliminating the need to maintain both virtual and physical addresses in the queues for locking purposes
Solution Approach 2:
The patent makes the register file universal by using it for both address generation and cache locking purposes. The same register file that generates addresses is also used to store locked addresses, eliminating the need for separate storage structures and reducing overall hardware area
2Reliability
If registers are added to manage lock addresses in L2 cache unit, then cache locking is enabled, but hardware complexity and area requirements increase
Solution Approach 1:
The patent merges the address management functions by using the existing register file for both address generation and cache locking. This consolidation eliminates separate locking structures and reduces the overall complexity of the L2 cache unit
Solution Approach 2:
The register file is designed to serve multiple purposes: generating addresses for memory access and storing addresses of data to be locked in the cache. This multi-functional approach reduces the need for dedicated locking hardware and simplifies the overall system architecture
3Reliability
If conventional cache locking mechanisms are implemented with full address maintenance, then data can be locked in cache, but performance decreases due to hardware overhead
Solution Approach 1:
The patent extracts only the essential locking information (address to be locked) from the full address maintenance requirement. By storing only the address in a register and using it to override the replacement algorithm, the system achieves cache locking without the performance penalty of maintaining complete address pairs in multiple queues
Solution Approach 2:
The patent changes the parameter representation from full virtual and physical address pairs to simplified address registers. This parameter reduction allows the cache locking mechanism to operate with less hardware overhead and improved performance while maintaining the ability to retain critical data in the cache
Data Source
AI summary
Systems and methods for the implementation of more efficient cache locking mechanisms are disclosed. These systems and methods may alleviate the need to present both a virtual address (VA) and a physical address (PA) to a cache mechanism. A translation table is utilized to store both the address and the locking information associated with a virtual address, and this locking information is passed to the cache along with the address of the data. The cache can then lock data based on this information. Additionally, this locking information may be used to override the replacement mechanism used with the cache, thus keeping locked data in the cache. The translation table may also store translation table lock information such that entries in the translation table are locked as well.