Programmable IC Cache Locking for Virtual On-Chip Memory
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Solution Overview
Problem
Programmable integrated circuits (ICs) often have limited on-chip memory resources, which can restrict their performance and flexibility, especially when compared to dedicated FPGA ICs, leading to a trade-off between cost and performance.
Innovation Solution
Implementing a virtual memory block within the programmable logic subsystem of a programmable IC, where a cache is locked to a subset of the memory address space, bypassing updates to physical memory and enhancing on-chip memory capacity by dedicating cache storage to the virtual memory block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If an SOC includes more on-chip memory resources to accommodate applications requiring greater memory capacity, then the memory capacity and performance are improved, but the cost of the SOC increases
Solution Approach 1:
The cache memory is designed to serve dual purposes: functioning as a standard cache for processor operations and simultaneously serving as virtual memory when locked to specific address spaces. This multi-functionality allows the same physical memory resources to provide both caching benefits and expanded memory capacity, eliminating the need for separate dedicated memory structures and reducing overall cost.
Solution Approach 2:
The system dynamically configures cache behavior through lock bits that can be programmed to lock cache ways to specific address spaces. This dynamic reconfiguration allows the cache to adapt between different operating modes (standard caching vs. virtual memory) based on runtime requirements, providing flexible memory management without requiring additional hardware resources.
2Productivity
If the quantity of programmable logic resources on an SOC is increased to match dedicated FPGA capabilities, then the processing performance and flexibility are improved, but the available on-chip memory resources decrease
Solution Approach 1:
The cache memory structure is utilized for dual purposes: serving as traditional cache memory for high-speed data access and as virtual memory when address spaces are locked to cache ways. This eliminates the need for separate dedicated memory structures, providing expanded memory capacity without requiring additional silicon real estate that would compete with programmable logic resources.
Solution Approach 2:
The virtual memory implementation creates a mapping between cache storage and external memory address spaces. When a cache way is locked to a virtual address space, the cache effectively creates a copy of that external memory space in the faster cache memory, providing the benefits of both large external memory capacity and fast cache access speeds.
3Quantity of substance
If cache memory is used for virtual memory addressing, then the effective memory capacity is improved, but cache coherency maintenance becomes more complex
Solution Approach 1:
The cache is divided into multiple independent ways, each of which can be independently locked to different address spaces. This segmentation allows different portions of the cache to serve different functions simultaneously - some ways can maintain virtual memory mappings while others continue to function as traditional caches, and coherency protocols can be applied selectively to each segment based on its current purpose.
Solution Approach 2:
Different cache ways can have different coherency requirements based on their current function. When a cache way is locked to a virtual address space, coherency protocols are applied to that specific way. When the same way is unlocked and used as traditional cache, different coherency rules apply. This localized approach to coherency management reduces overall system complexity compared to applying uniform coherency protocols to the entire cache.
4Quantity of substance
If cache storage is dedicated to virtual memory block, then the on-chip memory availability is improved, but the cache access latency may increase
Solution Approach 1:
The cache configuration is dynamic and can be reprogrammed at runtime. Cache ways that are not currently needed for virtual memory mappings can be unlocked and reused as traditional cache memory, providing fast access for frequently used data. This dynamic reconfiguration allows the system to optimize for speed when virtual memory is not needed and for capacity when it is needed, minimizing the impact on access latency.
Solution Approach 2:
Not all cache ways need to be locked to virtual address spaces simultaneously. The system can lock only the minimum number of cache ways required to provide the needed virtual memory capacity, leaving the remaining cache ways available for traditional high-speed caching operations. This partial locking approach ensures that sufficient cache capacity remains available for time-critical data access, minimizing latency impact.
Data Source
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AI summary
An approach for management of memory in a programmable integrated circuit (IC) (100) includes configuring (602) a memory map (400) of the programmable IC with an association of a first subset of addresses of memory address space of the programmable IC and physical memory of the programmable IC. The memory map is further configured (602) with an association of a second subset of addresses of the memory address space and a virtual memory block (1 12). At least a portion of a cache memory of the programmable IC is locked (608, 612, 616) to the second subset of addresses.