Cache Lockout Control for Hardware Failure Detection
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Solution Overview
Problem
Conventional data processing devices face inaccuracies in determining hardware failures due to cache line lockout indicators being reset during cache invalidation events, leading to incorrect assessment of error-prone cache lines.
Innovation Solution
Implementing a programmable lockout reset policy that maintains or resets lockout bits based on a cache control register, allowing memory error management software to accurately identify hardware failures and flexibly manage polling intervals, while ensuring data validity bits are reset during cache invalidation events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If lockout bits are reset during cache invalidation events, then cache can be fully invalidated and reused, but hardware failure detection accuracy deteriorates due to loss of error state information
Solution Approach 1:
The patent segments the cache state management by introducing separate lockout bits distinct from data validity bits. This segmentation allows independent tracking of error conditions (lockout bits) separate from cache line validity (valid bits), enabling selective preservation of error information during cache invalidation while maintaining proper cache functionality.
Solution Approach 2:
The patent implements preliminary action by setting lockout bits before cache invalidation occurs. When an error is detected in a cache line, the lockout bit is set in advance to mark the line as erroneous. This preliminary marking ensures that even when the cache is later invalidated and reused, the historical error information is preserved and can be used to detect hardware failures.
2Measurement precision
If lockout states are maintained during cache invalidation, then hardware failure detection accuracy is improved, but cache management complexity increases
Solution Approach 1:
The patent extracts the error tracking function from the general cache management by introducing dedicated lockout bits. This extraction separates the concern of tracking hardware errors from the broader cache invalidation and management operations, simplifying the overall system by giving error tracking its own dedicated mechanism rather than embedding it within general cache control logic.
Solution Approach 2:
The lockout bits serve as an intermediary between error detection and cache management. Rather than directly managing error states within the main cache control flow, the lockout bits act as an intermediate layer that records error information independently. This intermediary mechanism simplifies cache management by providing a clear, separate indicator of erroneous cache lines that can be handled independently from general cache operations.
3Ease of operation
If polling intervals are fixed, then error monitoring is simplified, but flexibility in error management is reduced
Solution Approach 1:
The patent implements dynamics by making the polling interval configurable rather than fixed. The system allows the polling interval to be dynamically adjusted based on operational needs, enabling longer intervals during normal operation to reduce overhead and shorter intervals when error detection is critical. This dynamic adjustment provides both simplicity (through configurable defaults) and flexibility (through adaptability to different operational contexts).
Data Source
AI summary
Each cache line of a cache has a lockout state that indicates whether an error has been detected for data accessed at the cache line, and also has a data validity state, which indicates whether the data stored at the cache line is representative of the current value of data stored at a corresponding memory location. The lockout state of a cache line is indicated by a set of one or more lockout bits associate with the cache line. In response to a cache invalidation event, the state of the lockout indicators for each cache line can be maintained so that locked out cache lines remain in the locked out state even after a cache invalidation. This allows memory error management software executing at the data processing device to robustly manage the state of the lockout indicators.