Processor Cache Lookup Table Sizing for Cryptographic Performance
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Solution Overview
Problem
Conventional technologies do not yield good software cryptographic performance on aggressive chip multithreading processors, which are poorly suited for computationally intensive cryptographic operations like encryption and decryption due to high memory latency and resource competition.
Innovation Solution
Increasing the size of lookup tables to fit within the processor cache, allowing for optimized execution of cryptographic operations by reducing the number of arithmetic logic unit operations and improving memory access efficiency, thereby enhancing performance on chip multithreading processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional cryptographic operations are executed on aggressive chip multithreading processors, then multithreading capability is utilized, but cryptographic performance deteriorates due to high CPI and memory stalls
Solution Approach 1:
The patent pre-computes cryptographic lookup tables and stores them in processor cache before execution. This preliminary action prepares the data in advance, allowing the processor to perform cryptographic operations without real-time computation delays, thus resolving the contradiction between multithreading capability and cryptographic performance
Solution Approach 2:
The patent changes the parameter of lookup table size to fit within processor cache memory constraints. By optimizing the table size parameter, the system achieves both efficient cache utilization and high cryptographic throughput, enabling aggressive chip multithreading to effectively process cryptographic workloads
2Speed
If lookup tables are increased in size to improve cryptographic operation speed, then memory access efficiency improves, but cache memory capacity is exceeded
Solution Approach 1:
The patent optimizes the lookup table size parameter to precisely fit within the processor cache capacity. This parameter adjustment ensures that the tables are large enough to provide efficient cryptographic operations but small enough to remain entirely within cache memory, achieving both fast access and proper utilization of available memory resources
3Productivity
If multiple lookup tables are combined into a single table, then the number of memory accesses decreases, but the resulting table size may exceed cache capacity
Solution Approach 1:
The patent combines multiple cryptographic lookup tables into a single unified table structure. This merging reduces the number of separate memory access operations required during cryptographic processing, improving productivity while the combined table is sized to fit within cache memory
Solution Approach 2:
The patent adjusts the parameter of the combined lookup table size to ensure it fits within cache memory constraints. By carefully controlling the table size parameter, the system achieves reduced memory access operations while maintaining the combined table within available cache capacity
Data Source
AI summary
Improved performance of a chip multithreading (CMT) processor during processing of a cipher is disclosed. The chip multithreading processor may be located on a chip multithreading processor chip that includes a processor cache. The selection of a cipher is received. The cipher is processed by executing a plurality of cryptographic operations on the chip multithreading processor. Lookup tables used during the execution of the plurality of cryptographic operations are determined. The size of at least one of the lookup tables may be increased, such that the at least one lookup table is able to be stored in a processor cache located on the chip multithreading processor chip. Further adjustments may be made to the size of one or more lookup tables depending on the cipher selected, other operations executing on the chip multithreading processor, or both.