Semiconductor Package Layout for Faster Cache-to-Main Memory Access
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Solution Overview
Problem
Existing 3D-IC packages face challenges in increasing communication speed between cache memory dies and main memory dies.
Innovation Solution
A semiconductor package design that includes a logic die, a cache memory die with a redistribution layer (RDL) for enhanced wiring, a main memory die stack structure vertically aligned, an inactive element, and a mold covering the sidewalls and surfaces of the main memory dies and inactive element.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If main memory dies are stacked vertically on cache memory die to increase communication speed, then communication speed between cache and main memory is improved, but the planar area occupied by main memory dies increases
Solution Approach 1:
The patent transitions from horizontal arrangement to vertical stacking of main memory dies, utilizing the third dimension (height) to accommodate multiple memory dies. This dimensional change allows increased memory capacity and communication speed without proportionally increasing the planar footprint, as dies are stacked in the vertical direction rather than spread out horizontally.
Solution Approach 2:
The patent implements a stacked configuration where main memory dies are nested vertically on top of the cache memory die, similar to nested dolls. This nesting approach allows multiple functional layers to occupy the same or overlapping planar projections, thereby reducing the total planar area required while maintaining high-speed communication pathways through vertical interconnects.
2Use of energy by moving object
If inactive element is added on cache memory die for power supply, then power supply efficiency is improved, but the planar area of cache memory die increases
Solution Approach 1:
The patent introduces an inactive element with specific local functionality (power supply) positioned at a particular location on the cache memory die. This inactive element provides localized power distribution to the stacked main memory dies without requiring modifications across the entire cache die area, thereby improving power supply efficiency while minimizing the additional planar area consumed.
3Strength
If mold covers sidewalls of main memory dies and inactive element, then structural protection is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the protective mold structure into distinct segments: one portion covering the sidewalls of stacked main memory dies and another portion covering the inactive element on the cache memory die. This segmentation allows the mold to be applied in manageable sections, potentially simplifying the manufacturing process while providing comprehensive structural protection to both the vertical stack and the horizontal inactive element.
Data Source
AI summary
A semiconductor package includes a logic die having a first planar area, a cache memory die on the logic die and having the first planar area, a main memory die stack structure on the cache memory die and including main memory dies stacked in a vertical direction and having a second planar area smaller than the first planar area, and a mold on the cache memory die and covering sidewalls of the main memory dies.