Cache Management Engine for LTE RACH Memory Bandwidth Optimization
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Solution Overview
Problem
In 4G cellular communication systems like LTE, the RACH process requires significant memory throughput for storing all radio signal data, even though only partial data is necessary for batch processing, leading to inefficient use of memory bandwidth.
Innovation Solution
A processor device with a cache management engine (CME) that selectively invalidates and transfers only relevant data samples from the local buffer to the system memory, reducing redundant data transfer and optimizing memory usage by detecting symbol boundaries and managing data coherence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all radio signal data is transferred and stored in system memory for batch processing, then data availability for processing is ensured, but memory bandwidth is wasted due to transferring redundant data
Solution Approach 1:
The patent extracts only the necessary data samples from the local buffer to the system memory, rather than transferring all data. The cache management engine identifies and transfers only those data samples that are required for batch processing, leaving redundant data in the local buffer. This extraction principle directly reduces memory bandwidth consumption while ensuring data availability for processing.
Solution Approach 2:
The patent segments the data transfer process into two distinct paths: necessary data samples are transferred to system memory, while redundant data samples remain in the local buffer. This segmentation allows the system to selectively manage data based on processing requirements, optimizing memory bandwidth usage without compromising the availability of required data.
2Speed
If a large local buffer is used to store all radio signal data, then data access speed is improved, but device complexity and memory requirements increase
Solution Approach 1:
The patent divides the buffer storage into two levels: a smaller local buffer for fast access to recently processed data, and system memory for long-term storage of necessary data. This segmentation eliminates the need for a single large buffer, reducing device complexity while maintaining fast data access speeds for active processing through the local buffer.
Solution Approach 2:
The cache management engine acts as an intermediary between the local buffer and system memory, intelligently managing data transfer based on processing needs. This intermediary layer allows the system to use a smaller local buffer while still ensuring that necessary data is available in system memory, thereby reducing device complexity without sacrificing data access efficiency.
3Reliability
If redundant data is transferred to system memory, then data coherence is maintained, but power consumption increases
Solution Approach 1:
The cache management engine extracts only the necessary data samples from the local buffer to the system memory, avoiding the transfer of redundant data. This selective extraction maintains data coherence for processing while significantly reducing the energy consumption associated with memory transfer operations, as fewer data samples are moved across the memory interface.
4Productivity
If all data is kept in local buffer, then processing speed is maintained, but the need for large on-chip SRAM increases
Solution Approach 1:
The patent segments data storage between local buffer and system memory, allowing the system to maintain high processing speed through the local buffer while storing less frequently accessed data in system memory. This segmentation eliminates the need for large on-chip SRAM capacity, as only essential data needs to be retained in the faster local buffer during active processing.
Solution Approach 2:
The cache management engine extracts only the necessary data samples from the local buffer to system memory, allowing the local buffer to be smaller since it doesn't need to hold all data indefinitely. This extraction approach maintains processing speed by keeping active data in the local buffer while reducing the overall SRAM capacity requirement.
Data Source
AI summary
A processor device processes data samples of a radio signal in a mobile communication system. A fast flow process is executed for all samples and a batch process is executed at intervals on a subset of the samples. The device has a processor for executing the flow process via a local buffer memory, a memory interface to a system memory, and a memory controller for controlling storing of the data samples in the buffer memory. The processor establishes whether data samples in the local buffer memory are part of the subset, and if not, invalidates them after executing the flow process. The memory controller provides free memory space in the local buffer by transferring data samples which are not invalidated from the local buffer memory to the system memory, and by invalidating processed samples. Advantageously the local buffer may be relatively small, while the amount of data transferred to the system memory is limited.