Integrated Cache Manager Using Memory Buckets for NAND Write Performance

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Solution Overview

Problem

Current systems using NAND flash memory as a second-level memory for data evicted from high-performance first-level memory, such as DRAM, face performance issues due to inefficient processing of small random writes, which require frequent garbage collection processes.

Innovation Solution

Organizing flash memory into distinct regions called buckets, each with a separate buffer to aggregate small writes into larger objects for sequential writing, and maintaining access counts to prioritize 'hotter' data, allowing more frequent access and reducing the need for garbage collection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If flash memory is used as second-level memory for data evicted from first-level memory, then storage capacity is expanded at lower cost, but write performance deteriorates due to frequent garbage collection processes

Engineering Contradiction:
Improvestorage capacityVSAvoidwrite performance
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The flash memory device is divided into multiple buckets, each representing a distinct region. This segmentation allows independent management of data blocks, enabling more efficient garbage collection by confining it to specific buckets rather than the entire memory space, thus improving write performance while maintaining expanded storage capacity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A buffer is introduced as an intermediary component between the first-level memory and the flash memory buckets. The buffer temporarily holds data before it is written to flash memory, allowing for aggregation of small writes into larger sequential writes, which significantly improves write performance by reducing the frequency of garbage collection operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If small random writes are processed frequently in flash memory, then data access flexibility is improved, but garbage collection overhead increases

Engineering Contradiction:
Improvedata access flexibilityVSAvoidgarbage collection overhead
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

Data is preliminarily stored in a buffer before being written to flash memory buckets. This preliminary action allows small random writes to be aggregated and reorganized into larger sequential writes, maintaining data access flexibility while significantly reducing garbage collection overhead by minimizing the number of write operations to flash memory.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Instead of immediately writing each small random write to flash memory, the system uses periodic action by batching multiple writes in the buffer and consolidating them into larger sequential writes at intervals. This periodic consolidation reduces the frequency of garbage collection operations while maintaining the flexibility to handle random write requests.

Inventive Principle:
Principle #19Periodic action

3Productivity

If data is frequently moved between buckets based on access counts, then cache efficiency is improved, but system complexity increases

Engineering Contradiction:
Improvecache efficiencyVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system implements feedback by tracking access counts for data in each bucket and using this information to make intelligent decisions about data movement. When data access patterns indicate that data is frequently accessed (hot data), it can be moved to higher-priority buckets or promoted to first-level memory, improving cache efficiency. The feedback mechanism uses simple access count thresholds rather than complex algorithms, keeping system complexity manageable.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system changes parameters by using access count thresholds as a simple metric to determine data movement between buckets. Instead of complex cache replacement algorithms, the system adjusts the access count parameter to trigger promotions or demotions of data, achieving improved cache efficiency through a relatively simple parameter-based approach that maintains low system complexity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11977483B2Maintaining data in a first level memory and buckets representing regions of memory devices to extend data cache
Publication Date: 2024.05.07 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11977483B2 patent drawing
  • US11977483B2 patent drawing
  • US11977483B2 patent drawing

AI summary

Provided are a computer program product, integrated cache manager, and method for maintaining data in a first level memory and buckets representing regions of memory devices to extend data cache. A plurality of buckets represent distinct regions of memory devices. The buckets are associated with different threshold access count ranges. Data having an access count is stored in one of the buckets associated with a threshold access count range including the access count of the data to store. Data evicted from a first level memory is copied to an initial bucket comprising one of the buckets. Data is moved from a source bucket comprising one of the buckets, including the initial bucket, to a target bucket of the buckets having a target threshold access count range including an access count of the data to move.