Cache Manager with Pointer Entries for DMA Data Transfer

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Solution Overview

Problem

Modern systems with multiple central processing units (CPUs) and software threads face challenges in managing DMA requests efficiently, particularly in preventing duplicate data transfers and ensuring different data is written to the same external storage location, due to the need for centralized management to determine data availability in local cache or memory.

Innovation Solution

A centralized management function and apparatus that includes a cache manager and search module to efficiently manage data access, utilizing a cache with pointer entries and search parameters to identify and store addresses of requested data items, allowing for efficient data retrieval and storage within a memory system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a centralized management function is implemented to determine data availability in local cache or memory, then data transfer accuracy and system reliability are improved, but device complexity increases

Engineering Contradiction:
Improvedata transfer accuracyVSAvoidmanagement function complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a cache manager as an intermediary component that mediates between DMA modules and local cache/memory. The cache manager receives DMA requests, checks the cache tag array for data availability, and coordinates data transfer operations. This intermediary structure improves data transfer accuracy by centralizing management logic while containing complexity within a dedicated management module rather than distributing it throughout the entire system.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The cache manager implements self-service mechanisms by autonomously checking the cache tag array to determine whether requested data is already present in local cache or memory. The system performs self-validation through tag comparison and automatically initiates appropriate transfer operations without requiring external intervention, thereby improving reliability while maintaining manageable complexity through automated decision-making.

Inventive Principle:
Principle #25Self-service

2Productivity

If DMA operations serve multiple CPUs and software threads simultaneously, then system productivity and resource utilization are improved, but the difficulty of detecting and measuring data availability increases

Engineering Contradiction:
Improvesystem throughputVSAvoiddata availability detection
Core Design Contradiction:
ProductivityVSDifficulty of detecting and measuring

Solution Approach 1:

The cache management structure is segmented into distinct components: a tag array for storing data identifiers, a data array for storing actual data, and a cache manager for coordination. This segmentation allows multiple CPUs and threads to access different segments simultaneously while the cache manager efficiently detects data availability by checking only the relevant tag entries, reducing the complexity of detecting and measuring data availability in a multi-processor environment.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary actions by pre-loading data into local cache or memory and pre-establishing the cache tag array with data identifiers before DMA transfer operations begin. This preliminary organization of data and metadata enables rapid detection of data availability during concurrent DMA operations, allowing the cache manager to quickly determine whether requested data is already present without complex real-time analysis.

Inventive Principle:
Principle #10Preliminary action

3Speed

If data is cached in local memory with pointer entries, then data access speed is improved, but memory space requirements increase

Engineering Contradiction:
Improvedata access speedVSAvoidcache memory size
Core Design Contradiction:
SpeedVSVolume of stationary object

Solution Approach 1:

The cache structure implements local quality by organizing memory into specialized regions: a compact tag array for storing data identifiers and pointers, and a data array for storing actual cached data. This localized organization optimizes space utilization by storing only necessary metadata (tags) in the tag array, enabling fast data access through pointer-based retrieval while minimizing overall cache memory requirements compared to duplicating full data copies.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system uses copying by creating compact pointer entries in the tag array that reference data locations rather than duplicating entire data items. Each tag entry contains a pointer or offset to the actual data in the data array, allowing the cache to maintain high access speed through direct pointer lookup while significantly reducing memory space requirements compared to storing complete data copies for every cached item.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS9514060B2Device, system and method of accessing data stored in a memory
Publication Date: 2016.12.06 ENTROPIC COMM INC
  • US9514060B2 patent drawing
  • US9514060B2 patent drawing
  • US9514060B2 patent drawing

AI summary

Device, system and method of accessing data stored in a memory. For example, a device may include a memory to store a plurality of data items to be accessed by a processor; a cache manager to manage, a cache within the memory, the cache including a plurality of pointer entries, wherein each pointer entry includes an identifier of a respective data item and a pointer to an address of the data item; and a search module to receive from the cache manager an identifier of a requested data item, search the plurality of pointer entries for the identifier of the requested data item and, if a pointer entry is detected to include an identifier of a respective data item that matches the identifier of the requested data item then, provide the cache manager with the pointer from the detected entry. Other embodiments are described and claimed.