Set-Associative Cache Mapper Circuit for Address Mapping
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Solution Overview
Problem
Set-associative (SA) caches face inefficiencies in mapping memory addresses to cache sets, leading to underutilization when access patterns are non-uniform, particularly in strided access scenarios, where conventional methods fail to optimize cache usage and result in significant unused cache capacity.
Innovation Solution
A programmable mapper circuit employing modulo-arithmetic and multiplexer operations, based on cache size decompositions into prime factors, to compute cache locations efficiently across various cache configurations, ensuring optimal utilization of cache sets by selecting and combining modulus results to determine cache locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional mapping methods are used in set-associative caches, then the hardware design is simple, but cache utilization is poor under non-uniform access patterns
Solution Approach 1:
The patent implements a dynamic mapping system where the cache controller can switch between different mapping equations (e.g., direct mapping, set-associative mapping, fully associative mapping) based on the detected access pattern. This allows the cache to adapt its behavior to different workloads, improving utilization without permanently increasing hardware complexity through fixed complex structures
Solution Approach 2:
The system changes mapping parameters (such as the mapping equation or associativity level) dynamically based on access pattern analysis. By adjusting these parameters in response to workload characteristics, the cache achieves better utilization across diverse access patterns without requiring a completely complex hardware design for every scenario
2Adaptability or versatility
If fixed mapping equations are used, then the hardware design is simple, but the cache cannot adapt to different cache sizes and access patterns
Solution Approach 1:
The patent employs a universal mapping apparatus that can compute multiple different mapping equations using the same hardware resources. The mapper circuit is designed to support various cache configurations (different sizes, associativities) by selecting and executing appropriate mapping equations, making the hardware multi-functional without requiring separate dedicated circuits for each configuration
Solution Approach 2:
The mapping equation selection is made dynamic based on the cache configuration and access patterns. The system can reconfigure which mapping equation is used without physical hardware changes, allowing adaptation to different cache sizes and scenarios while maintaining reasonable hardware complexity through software or control logic management
3Measurement precision
If modulo operations are performed for each cache set, then accurate cache location mapping is achieved, but the computing resources and time are excessive
Solution Approach 1:
The patent segments the cache into banks and uses a hierarchical mapping approach where the mapping equation first determines which bank to access, then subsequent operations determine the specific set within that bank. This segmentation allows modulo operations to be performed on smaller values rather than the entire cache space, reducing computation time while maintaining mapping accuracy
Solution Approach 2:
The system performs preliminary analysis of the access pattern to determine the appropriate mapping equation before actual cache access. By pre-computing or pre-selecting the mapping parameters based on workload characteristics, the system avoids performing complex modulo operations in real-time during cache access, thereby reducing computation time while maintaining accuracy
Data Source
AI summary
A circuit and corresponding method map memory addresses onto cache locations within set-associative (SA) caches of various cache sizes. The circuit comprises a modulo-arithmetic circuit that performs a plurality of modulo operations on an input memory address and produces a plurality of modulus results based on the plurality of modulo operations performed. The plurality of modulo operations performed are based on a cache size associated with an SA cache. The circuit further comprises a multiplexer circuit and an output circuit. The multiplexer circuit outputs selected modulus results by selecting modulus results from among the plurality of modulus results produced. The selecting is based on the cache size. The output circuit outputs a cache location within the SA cache based on the selected modulus results and the cache size. Such mapping of the input memory address onto the cache location is performed at a lower cost relative to a general-purpose divider.