Cache Memory Bandwidth Optimization via Reference Size Alignment

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Computing devices face inefficiencies in memory bandwidth usage, leading to increased power consumption when accessing memory for data processing, particularly due to the need for error detection and correction using parity information.

Innovation Solution

Implementing a computing device with a cache memory system that caches data and parity information, allowing for efficient bandwidth utilization by storing and outputting data in reference sizes matching the main memory's communication units, thereby reducing the need for excessive bandwidth usage during write and read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the computing device accesses the main memory for data processing, then data processing capability is improved, but power consumption increases due to increased bandwidth usage

Engineering Contradiction:

Improvedata processing capabilityVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent divides the memory system into two segments: a main memory for storing data and parity information, and a cache memory for caching frequently accessed data. This segmentation allows the processor to access cached data without utilizing the main memory bandwidth, thereby reducing power consumption while maintaining data processing capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The cache memory pre-stores (caches) data that is likely to be accessed by the processor before actual access occurs. This preliminary action enables the processor to retrieve data from the fast cache memory instead of accessing the main memory, reducing bandwidth usage and power consumption during data processing operations.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If the computing device uses parity information for error detection, then data reliability is improved, but bandwidth usage increases

Engineering Contradiction:

Improvedata reliabilityVSAvoidbandwidth energy

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent combines data and parity information into a single memory structure, allowing the cache memory to cache both simultaneously. This merging enables the system to verify data integrity through parity checking without requiring separate bandwidth for parity operations, as both data and parity are readily available in the cache.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The cache memory acts as an intermediary between the processor and main memory, storing both data and parity information locally. This intermediary structure allows error detection and correction operations to be performed using cached parity information without accessing the main memory, thereby reducing bandwidth usage while maintaining data reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10783033B2Device and method for accessing in-band memory using data protection

Publication Date: 2020.09.22 SAMSUNG ELECTRONICS CO LTD

AI summary

A computing device includes a main memory, a processor, and a cache. The main memory stores data and parity, for checking an error of the data, and sends and receives the data and parity with a reference size. The processor accesses the main memory, and the cache memory caches the data. If the processor requests a write operation for current data, the current data are stored to the cache memory and the cache memory changes the stored current data to the reference size and outputs the current data changed to the reference size to the main memory. A size of the current data is smaller than the reference size.