Cache Memory Coherence via Extracted Tag Bits

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Solution Overview

Problem

Conventional cache memory systems experience delays due to the two-stage access of tags, which limits the machine cycle speed, especially as CPU processing speeds increase, due to the slow data transfer from the first level cache to the CPU.

Innovation Solution

A cache memory system that eliminates the need for a copy of the first level cache tag in the second level cache by storing a part of the first level cache information in the second level cache, allowing direct access to the first level cache status and maintaining coherence between the two caches using a coherence maintaining unit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the second level cache stores a copy of the first level cache tag to maintain coherence, then cache coherence is maintained, but the machine cycle speed decreases due to two-stage access delay

Engineering Contradiction:

Improvecache coherenceVSAvoidmachine cycle speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent extracts only the necessary coherence-maintaining information (valid bits and dirty bits) from the first level cache tag and stores them directly in the second level cache tag, rather than storing complete tag copies. This eliminates the two-stage access delay while maintaining cache coherence through the extracted essential information.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the tag information into essential coherence-maintaining components (valid bit, dirty bit) and non-essential components. Only the essential segments are stored in the second level cache to enable direct access, while avoiding the overhead of storing complete tag copies.

Inventive Principle:

Principle #1Segmentation

2Reliability

If the second level cache obtains registration information from the first level cache, then coherence is maintained, but processing delay increases

Engineering Contradiction:

Improvecache coherenceVSAvoidprocessing delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary action by pre-storing the essential coherence information (valid and dirty bits) from the first level cache into the second level cache tag during the write-back process. This preliminary storage eliminates the need for subsequent registration information retrieval, reducing processing delay while maintaining coherence.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If complete tag copies are stored in the second level cache, then coherence information is complete, but material requirements increase

Engineering Contradiction:

Improvecoherence information completenessVSAvoidmemory capacity

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies local quality by storing different types of information in different cache levels: complete tags in the first level cache and only essential coherence information (valid bit, dirty bit) in the second level cache. This differentiated storage approach maintains coherence information completeness where needed while reducing overall material requirements.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS7428617B2Cache memory and method to maintain cache-coherence between cache memory units

Publication Date: 2008.09.23 FUJITSU LTD

AI summary

A cache memory includes a first-level cache-memory unit that stores data; a second-level cache-memory unit that stores data that is same as the data stored in the first-level cache-memory unit; a storage unit that stores a part of information relating to the first-level cache-memory unit; and a coherence maintaining unit that maintains cache-coherence between the first-level cache-memory unit and the second-level cache-memory unit based on information stored in the storage unit.