Cache Memory Control Apparatus for Multi-Core Latency Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-core semiconductor integrated circuits, cache misses lead to increased latency and power consumption due to complex wiring requirements for direct connections between cores and main storage units, which complicates data acquisition and is not practical for downsized systems.
Innovation Solution
A cache memory control apparatus with a computing processing unit, connecting unit, control unit, and data bus that transfers data from the main storing unit to the cache memory and processor core, optimizing data transfer by executing READ and MOVE-IN operations in a pipeline process, reducing the need for additional wiring and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transferred from main storing unit to cache memory through direct connection, then data acquisition speed is improved, but wiring complexity and circuit size increase
Solution Approach 1:
The patent introduces a buffer as an intermediary component between the main storing unit and cache memory. The buffer temporarily stores data during transfer, allowing the system to achieve fast data acquisition without requiring complex direct wiring between all components. This mediator approach resolves the contradiction by providing a simpler wiring structure that maintains high-speed data transfer capability.
2Loss of time
If direct connection between main storing unit and cache memory is implemented, then latency is reduced, but circuit size increases
Solution Approach 1:
The patent merges the buffer function into the existing cache memory structure, combining multiple functions (data transfer buffer, cache storage, and output buffer) into a single integrated component. This merging approach reduces the overall circuit size compared to implementing separate direct connection paths, while still achieving reduced latency through optimized data transfer and simultaneous READ/MOVE-IN operations.
Solution Approach 2:
The patent implements preliminary action by pre-fetching data from the main storing unit to the buffer before it is actually needed by the cache memory. This allows data to be ready for immediate transfer, reducing latency without requiring complex real-time wiring. The buffer is prepared in advance, enabling faster data acquisition when needed.
3Productivity
If complex wiring for direct connection is used, then data transfer efficiency is improved, but power consumption increases
Solution Approach 1:
The buffer acts as an energy-efficient intermediary that enables efficient data transfer without requiring continuous high-power direct connections. By temporarily storing data in the buffer, the system can transfer data in optimized batches, reducing the overall power consumption compared to maintaining complex direct wiring paths that would require constant energy for signal transmission across multiple components.
Data Source
AI summary
An apparatus for controlling a cache memory that stores therein data transferred from a main storing unit includes a computing processing unit that executes a computing process using data, a connecting unit that connects an input portion and an output portion of the cache memory, a control unit that causes data in the main storing unit to be transferred to the output portion of the cache memory through the connecting unit when the data in the main storing unit is input from the input portion of the cache memory into the cache memory, and a transferring unit that transfers data transferred by the control unit to the output portion of the cache memory, to the computing processing unit.