Cache Memory Control Method for Power Reduction
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Solution Overview
Problem
In multiprocessor and multithread processing systems, shared cache memory access results in wasteful power consumption due to simultaneous hit/miss determination across all ways, especially when the probability of a cache hit is high for allocated ways, leading to inefficient power usage.
Innovation Solution
Implement a cache memory control method that selectively allows or disallows cache refill for each memory unit, performing first cache hit/miss determination only on allowed units and ending access upon a cache hit, with optional second determination on disallowed or all units if a miss occurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If cache hit/miss determination is performed on all ways simultaneously, then cache accuracy is improved, but power consumption increases
Solution Approach 1:
The cache memory is divided into multiple ways, and the hit/miss determination process is segmented into two stages: first determining on allocated ways (high probability of hit) and then on other ways only if needed. This segmentation allows the system to perform accurate determination while reducing unnecessary power consumption on ways unlikely to be accessed.
Solution Approach 2:
Instead of performing complete hit/miss determination on all ways, the patent applies partial action by first checking only the allocated ways (which have high probability of cache hit) and reserving full examination of other ways for cases where the initial partial check fails. This reduces power consumption while maintaining sufficient accuracy.
2Reliability
If all ways are accessed for cache hit/miss determination, then cache reliability is improved, but power consumption increases
Solution Approach 1:
The patent performs preliminary hit/miss determination on allocated ways before proceeding to check other ways. This preliminary action filters out cases where the allocated way definitely contains the needed data, avoiding unnecessary power consumption on other ways while maintaining reliable cache operation.
Solution Approach 2:
The cache access strategy becomes dynamic rather than static: the system adapts its behavior based on the results of preliminary checks on allocated ways. If a hit is found in allocated ways, the system stops there; if not, it proceeds to check other ways. This dynamic approach optimizes power consumption while maintaining reliability.
3Use of energy by stationary object
If selective access to allocated ways is performed, then power consumption is reduced, but cache completeness may be compromised
Solution Approach 1:
The patent implements feedback mechanism where the result of hit/miss determination on allocated ways feeds back into the decision process for checking other ways. If the allocated way results in a cache hit, the feedback signals the system to stop checking other ways, saving power while maintaining complete cache coverage through the conditional check of other ways when needed.
Data Source
AI summary
An object of the present invention is to reduce power consumption accompanying a cache hit/miss determination. To achieve this object, when accessing a cache memory provided with a means for setting whether a cache refill to each way in the cache memory is allowed for each CPU or each thread, first, a first cache hit/miss determination is performed only on the way for which a refill is set to be allowed (Steps 2-1 and 2-2), and if the first cache hit/miss determination results in a cache hit, the access is ended (Step 2-6). In the case of a cache miss, the way for which a refill is not set to be allowed is accessed (Step 2-3), or a second hit/miss determination is performed by accessing all the ways (Step 2-4).