Cache Memory Data Packing for Mobile GPU Descriptor Indexing

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Solution Overview

Problem

Existing graphics and compute APIs, such as Vulkan, face challenges in efficiently supporting new features like Combined Resources Buffer and dynamic indexing on mobile GPU hardware, particularly in indexing thousands of descriptors in heterogeneous arrays.

Innovation Solution

A resource packing scheme is implemented where data resource descriptors of different types and sizes are arranged in cache memory, with a combined resource descriptor size and cache line size being integer multiples of each other, allowing for non-overlapping storage areas and grouping of descriptors by category, enabling efficient storage and retrieval.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If resource descriptors of different types and sizes are stored in cache memory without a structured packing scheme, then the cache memory can accommodate diverse resource types, but the indexing efficiency and retrieval performance deteriorate due to heterogeneous array management challenges

Engineering Contradiction:
Improvesupport for diverse resource typesVSAvoidindexing efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The cache memory is divided into multiple storage areas, each dedicated to storing resource descriptors of a specific type. This segmentation allows for organized storage of heterogeneous resource descriptors while enabling efficient indexing within each homogeneous storage area, resolving the contradiction between supporting diverse resource types and maintaining indexing efficiency

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each storage area is optimized with local indexing structures tailored to its specific resource descriptor type. This local optimization allows each storage area to operate independently with type-specific indexing strategies, improving overall indexing efficiency while maintaining the ability to handle diverse resource types across different storage areas

Inventive Principle:
Principle #3Local quality

2Productivity

If a packing scheme with integer multiple sizes is implemented, then storage organization and retrieval efficiency improve, but the complexity of determining and managing storage areas increases

Engineering Contradiction:
Improveretrieval efficiencyVSAvoidstorage area management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent establishes a parameter relationship where storage area sizes are integer multiples of a base unit size. This parameter constraint simplifies the management complexity by creating a regular, predictable storage structure that is easier to allocate and manage, while still achieving efficient retrieval through the organized packing scheme

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If resource descriptors are grouped by category in separate storage areas, then dynamic indexing and driver overhead are reduced, but the process of categorizing and organizing descriptors becomes more complex

Engineering Contradiction:
Improvedynamic indexing capabilityVSAvoiddescriptor organization process
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

Resource descriptors are pre-categorized and organized into appropriate storage areas before being used by the graphics processing unit. This preliminary organization reduces the complexity during runtime by having descriptors already sorted by category, enabling efficient dynamic indexing without requiring complex real-time categorization processes

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4111306B1Device and method for data packing in memory
Publication Date: 2024.11.27 HUAWEI TECH CO LTD
  • EP4111306B1 patent drawingFigure 1
  • EP4111306B1 patent drawingFigure 2(a)~3(c)
  • EP4111306B1 patent drawingFigure 4(a)~4(b)

AI summary

A data processor configured to arrange data and a set of data resource descriptors in a cache memory. The cache memory is linewise accessible by a data processing device. The data processor being configured to: determine a combined resource descriptor size and a cache line size such that one of those sizes is an integer multiple of the other; receive the data resource descriptors; define non-overlapping storage areas in the cache memory, each storage area being aligned to either (i) a line of the cache or (ii) a location offset from a line of the cache by an integer multiple of the determined combined resource descriptor size; form a series of groups of data resource descriptors, each group being of a size less than or equal to the combined resource descriptor size; and store each group of data resource descriptors in a respective one of the defined storage areas.