Cache Memory Data Routing for Parallel Computer Systems
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Solution Overview
Problem
In parallel computer systems, the efficiency of arithmetic operations is reduced due to communication delays caused by the arithmetic processing unit performing interruption processes when receiving data, leading to inefficient calculation processing speeds, especially when data not used for operations is stored in the cache memory, displacing essential data.
Innovation Solution
The system implements a method where the communication device determines whether received data is for caching or main memory storage based on control information, storing data intended for arithmetic operations directly in the cache memory and other data in the main memory, thereby preventing unnecessary data displacement and reducing communication delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the arithmetic processing unit performs interruption processes to receive data, then the communication device can store received data on the main memory, but the arithmetic processing unit experiences increased communication delay and reduced calculation processing efficiency
Solution Approach 1:
A reception buffer is introduced as an intermediary storage component between the communication device and the arithmetic processing unit. The buffer temporarily holds received data, allowing the arithmetic processing unit to retrieve data without performing interruption processes. This mediator decouples the data reception and arithmetic operation processes, eliminating communication delays while maintaining data reception reliability.
2Loss of time
If data is stored directly in the cache memory without discrimination, then communication delay is reduced, but data not used for operations displaces essential data, reducing arithmetic operation efficiency
Solution Approach 1:
The cache memory is differentiated into two distinct regions: a first cache region for storing data that will be used for arithmetic operations, and a second cache region for storing received data. This local quality differentiation ensures that essential operational data and received data do not compete for the same storage space, preventing displacement of critical data while maintaining fast access speeds for both data types.
3Loss of time
If a buffer for receiving data is provided on the arithmetic processing unit, then communication delay is reduced, but the device complexity increases due to additional components
Solution Approach 1:
The reception buffer is merged with the existing cache memory structure, utilizing the cache memory's fast access capabilities while repurposing part of its capacity for buffer functionality. This merging approach eliminates the need for a separate buffer component, reducing device complexity while still achieving the goal of reduced communication delay through direct arithmetic processing unit access to received data.
Data Source
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Figure 3
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AI summary
An information processing apparatus(2) included in a parallel computer system(1) has a memory(6) that holds data and a processor(3) including a cache memory(5) that holds a part of the data held on the memory(6) and a processor core(4) that performs arithmetic operations using the data held on the memory(6) or the cache memory(5). Moreover, the information processing apparatus(2) has a communication device(10) that determines whether data received from a different information processing apparatus(2a) is data that the processor core(4) waits for. When the communication device(10) determines that the received data is data that the processor core(4) waits for, the communication device(10) stores the received data on the cache memory(5). When the communication device(10) determines that the received data is data that the processor core(4) does not wait for, the communication device(10) stores the received data on the memory(6).