Cache Memory Fault Tolerance via Hierarchical Error Detection
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Solution Overview
Problem
Cache memory errors due to external factors can lead to incorrect instruction interpretation and data retrieval by processors, necessitating error recovery or reporting mechanisms to maintain system integrity.
Innovation Solution
A cache memory structure with a first and second layer cache, each equipped with parity check bits and error correction codes, along with a fault tolerance unit that determines error recoverability and generates signals for error reporting or recovery, including error type classification and request signals for main memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection and correction mechanisms are added to cache memory, then reliability is improved, but device complexity increases
Solution Approach 1:
The cache memory is divided into two distinct layers: L1 cache with parity check bits for quick error detection, and L2 cache with ECC bits for comprehensive error correction. This segmentation allows each layer to handle different types of errors with appropriate complexity, improving overall reliability without uniformly increasing complexity across the entire system.
Solution Approach 2:
The patent introduces a hierarchical dimension to error handling by implementing multiple cache layers with progressively more sophisticated error correction capabilities. The L1 cache handles simple parity errors while L2 cache handles complex ECC errors, adding a dimensional approach to error management that scales reliability without linearly increasing complexity.
2Reliability
If multiple cache layers with error correction are implemented, then fault tolerance is improved, but manufacturing precision requirements increase
Solution Approach 1:
Different error correction mechanisms are applied to different cache layers based on their specific requirements. The L1 cache uses simpler parity check bits suitable for its speed-critical function, while the L2 cache employs more robust ECC bits appropriate for its capacity-critical role. This local quality approach optimizes fault tolerance without uniformly demanding high manufacturing precision across all components.
3Reliability
If error recovery mechanisms are added to cache memory, then reliability is improved, but ease of operation decreases
Solution Approach 1:
The cache memory system implements autonomous error detection and recovery mechanisms that operate automatically without requiring external intervention. The fault tolerance unit continuously monitors for errors using parity and ECC bits, and automatically initiates recovery procedures by accessing main memory when errors are detected, maintaining ease of operation while improving reliability.
Solution Approach 2:
The system incorporates feedback mechanisms where error detection results from parity and ECC checks automatically trigger appropriate recovery actions. The fault tolerance unit receives error status feedback and responds by initiating main memory access for data recovery, creating a closed-loop system that improves reliability without increasing operational complexity for the user.
Data Source
AI summary
The exemplary embodiments of the invention relates to fault tolerance of a cache memory which recovers an error occurred in the cache memory or reports an error. A cache memory may include a first layer cache configured to store data requested from a processor, together with a tag related to the data and parity check bits for detecting data error and tag error; a second layer cache configured to store data requested from the first layer cache, together with parity check bits and an error correction code(ECC) bit for detecting data error and tag error; and a fault tolerance unit configured to generate an error signal indicating whether the data error or tag error occurred in at least one of the first layer cache and the second layer cache is recoverable.