Cache Memory Partitioning for Power Optimization
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Solution Overview
Problem
Current cache memory systems in devices face challenges in reducing power consumption, particularly in volatile memory like DRAM, as frequent refresh operations drain battery resources, and existing methods either unnecessarily turn off or reduce refresh rates for all memory banks, leading to inefficiencies.
Innovation Solution
The solution involves physically partitioning cache memory into separate clean and dirty data partitions, allowing the cache memory controller to reduce or disable refresh operations for clean data banks, while maintaining normal refresh rates for dirty data banks, thereby optimizing power usage during low power modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed frequently on all cache memory banks, then data integrity is maintained, but power consumption increases
Solution Approach 1:
The cache memory is divided into two separate partitions: a clean data partition and a dirty data partition. This segmentation allows different refresh strategies to be applied to each partition, enabling power savings on the clean partition while maintaining data integrity through regular refreshes on the dirty partition.
Solution Approach 2:
Different refresh rates are applied to different partitions of the cache memory. The clean data partition operates at a reduced refresh rate or is disabled during low power modes, while the dirty data partition maintains normal refresh rates to ensure data integrity. This local differentiation resolves the contradiction by applying quality control only where necessary.
2Use of energy by moving object
If refresh rate is reduced or disabled for all memory banks to save power, then power consumption decreases, but data integrity is compromised
Solution Approach 1:
The cache memory is segmented into clean and dirty partitions, allowing selective refresh operations. The dirty partition continues to receive regular refreshes to maintain data integrity, while the clean partition can operate at reduced power modes without compromising overall system reliability.
Solution Approach 2:
The system applies different refresh quality levels to different partitions based on their data state. Dirty data requires high-quality refresh operations to maintain integrity, while clean data can tolerate reduced refresh rates, enabling localized quality control that balances power consumption and reliability.
3Use of energy by moving object
If clean data is moved between DRAM chips to save power, then power consumption decreases, but system complexity increases
Solution Approach 1:
The cache memory is segmented into clean and dirty partitions that can be independently managed. This segmentation enables selective power management where clean partitions can be placed in low power modes without requiring complex data migration protocols between chips, as the partitioning itself provides the mechanism for power optimization.
Data Source
AI summary
A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls refresh operation so that data refresh does not occur for clean data only banks or the refresh rate is reduced for clean data only banks. Partitions that store dirty data can also store clean data, however other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.