Cache Memory System for RAID Write Penalty Reduction

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Solution Overview

Problem

Cache memory systems face inefficiencies in data storage and retrieval due to the high computational cost and time consumption of small random write operations in RAID configurations, particularly the 'RAIDS Write Penalty', which is exacerbated by the need for pre-read data and parity operations.

Innovation Solution

Implementing a log-based RAID approach within a non-volatile, solid-state cache memory system that bundles data extents into larger chunks, allowing for whole-stripe data writing and reducing the number of write operations to non-volatile electromechanical memory systems, thereby minimizing the 'RAIDS Write Penalty' and enhancing performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If small random write operations are performed in RAID configurations, then data redundancy and reliability are improved, but computational cost and time consumption increase significantly

Engineering Contradiction:
Improvedata redundancyVSAvoidtime consumption
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent combines multiple small random write operations into a single larger write operation by buffering data in memory before writing to the RAID array. This merging approach maintains data redundancy benefits while significantly reducing the time consumption associated with multiple separate write operations to the electromechanical storage system.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary data preparation and buffering in memory before the actual RAID write operation. By pre-processing data and organizing it into optimal write patterns beforehand, the system reduces the computational burden and time required during the actual write operation to the RAID array.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If pre-read data and parity operations are performed for each write operation, then data integrity is improved, but computational burden increases

Engineering Contradiction:
Improvedata integrityVSAvoidcomputational burden
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent merges multiple write operations into a single operation, which allows parity calculations to be performed once for the combined data set rather than separately for each individual write. This significantly reduces the computational burden while maintaining data integrity through proper RAID parity generation.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent uses memory as an intermediary copy buffer between the host system and the RAID array. Data is copied to and processed in memory first, allowing computational intensive operations like parity calculation to be performed in the faster memory environment before a single consolidated write to the RAID system, reducing overall computational burden.

Inventive Principle:
Principle #26Copying

3Reliability

If multiple write operations are performed on non-volatile electromechanical memory system, then data is stored reliably, but performance decreases

Engineering Contradiction:
Improvedata storage reliabilityVSAvoidperformance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent combines multiple small write operations into a single larger write operation to the electromechanical memory system. This merging strategy maintains reliable data storage through proper RAID formatting and redundancy while dramatically improving performance by reducing the number of separate mechanical seek and write cycles required.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a memory buffer as an intermediary between the host system and the electromechanical RAID storage. This intermediary allows data to be prepared, processed, and consolidated in fast memory before a single optimized write operation to the slower electromechanical system, thereby improving overall productivity while maintaining storage reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8713254B1System and method for improving cache efficiency
Publication Date: 2014.04.29 EMC IP HLDG CO LLC
  • US8713254B1 patent drawing
  • US8713254B1 patent drawing
  • US8713254B1 patent drawing

AI summary

A method and computer program product for receiving a newly-received data portion for storing within a cache memory system. A determination is made concerning whether the newly-received data portion corresponds with at least one data portion previously written to a non-volatile, memory system. If the newly-received data portion does not correspond with at least one previously-written data portion, the newly-received data portion is stored within the cache memory system using a protected data storage methodology.