Cache Memory Row Hammer State Value Access Control
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Solution Overview
Problem
In memory systems, continuous access to memory cells can lead to data distortion due to electromagnetic interference, known as row hammering, which affects adjacent cells and results in data damage.
Innovation Solution
A memory system that stores the access number of each row line in a cache line's row hammer state value and manages access between main and cache memory devices based on this value, using an access selection bit to determine whether to access the main memory or the cache memory before data distortion occurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If continuous access is performed on memory cells, then access speed is improved, but data distortion occurs due to row hammering
Solution Approach 1:
The patent applies preliminary action by monitoring the access count of row lines in advance and proactively switching to cache memory before data distortion occurs. The system tracks the number of times each row line has been accessed and uses this information to predict when row hammering effects will manifest, allowing preventive measures to be taken before data integrity is compromised.
Solution Approach 2:
The patent introduces an intermediary mechanism by using the cache memory device as a mediator between the host and the main memory device. When row hammering is detected or predicted through access count monitoring, the system routes requests through the cache memory first, which acts as a buffer that prevents direct continuous access to the same row lines in the main memory, thereby reducing electromagnetic interference effects.
2Reliability
If access number of row line is monitored and cache memory is used, then data damage is prevented, but memory resource usage increases
Solution Approach 1:
The patent applies universality by making the cache memory device serve multiple functions: it acts as both a performance buffer for frequently accessed data and as a monitoring mechanism for row hammering detection. The cache memory is used to store not only data but also access count information, allowing the system to monitor row line access patterns without requiring separate dedicated monitoring hardware, thus reducing overall memory resource consumption.
Solution Approach 2:
The patent changes the parameter of memory access strategy based on the access count of row lines. The system dynamically adjusts the access path by changing from direct main memory access to cache memory access when the access count threshold is reached. This parameter change allows the system to maintain data integrity while optimizing memory resource usage by leveraging the existing cache memory structure for both performance and protection functions.
3Ease of operation
If row hammer state value is stored in cache line, then access management is improved, but cache line structure becomes more complex
Solution Approach 1:
The patent merges the row hammer state value storage function with the existing cache line structure. Instead of adding a completely separate monitoring mechanism, the system integrates the access count tracking into the cache line data structure itself. This merging approach allows the cache line to serve dual purposes: storing data and tracking access patterns, thereby simplifying the overall system architecture while improving access management capabilities.
Solution Approach 2:
The patent applies self-service by enabling the cache memory device to automatically monitor and track access counts of row lines without requiring external intervention. The cache line structure inherently records access information, and the system uses this self-generated data to make intelligent access decisions. This self-service mechanism simplifies access management by eliminating the need for separate complex monitoring and control systems.
Data Source
AI summary
A memory system includes: a main memory device configured to include a plurality of row lines; a cache memory device configured to include a plurality of cache lines for caching data stored in the row lines, each cache line including cache data, a row hammer state value for storing an access number of a corresponding row line, and an access selection bit set according to the row hammer state value; and a memory controller configured to control an access operation to be performed on one of the main memory device and the cache memory device, which is selected according to the access selection bit of a cache-hit cache line, in response to a request from a host.