Selective Cache Memory Scrubbing for Soft Error Mitigation
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Solution Overview
Problem
Caches in data processing systems are prone to increased soft error rates (SER) due to technological scaling and low power states, which can lead to data corruption and instability.
Innovation Solution
Implementing a memory scrubbing controller that dynamically adjusts the scrubbing rate for cache memory, scrubbing modified data more frequently than clean data to detect and correct errors, while maintaining a lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the cache memory is retained in a low power state during inactive state to reduce standby leakage power, then power consumption is reduced, but soft error rates increase
Solution Approach 1:
The patent implements dynamic memory scrubbing that adjusts the scrubbing rate based on cache state. When cache lines are in modified state, they are scrubbed more frequently even during low power states, while clean cache lines use reduced scrubbing rates. This dynamic adaptation resolves the contradiction by maintaining reliability for modified data while accepting reduced scrubbing for clean data during low power operation.
Solution Approach 2:
The patent applies different scrubbing rates to different cache lines based on their individual states. Modified cache lines receive higher scrubbing rates while clean cache lines receive lower scrubbing rates. This local differentiation allows the system to focus error prevention resources where they are most needed (modified data) while reducing overall power consumption during inactive states.
2Speed
If technology scaling is continued to improve performance, then processing speed increases, but bit cell sensitivity to soft errors increases
Solution Approach 1:
The patent performs memory scrubbing as a preliminary action to detect and correct soft errors before they can cause data corruption or system failures. By proactively scrubbing cache lines, especially modified ones, the system prevents errors from propagating, thus maintaining reliability despite increased bit cell sensitivity from technology scaling.
Solution Approach 2:
The patent uses error detection feedback from scrubbing operations to identify and correct soft errors. The scrubbing mechanism continuously monitors cache integrity and triggers corrective actions when errors are detected, creating a feedback loop that maintains system reliability despite the increased vulnerability of scaled-down bit cells.
3Reliability
If uniform high scrubbing rate is applied to all cache lines to maximize error detection, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies differentiated scrubbing rates based on cache line characteristics. Modified cache lines, which contain data not yet synchronized with main memory, receive higher scrubbing rates to ensure error detection. Clean cache lines, which already match main memory, receive lower scrubbing rates. This local quality differentiation maintains error detection capability where needed while reducing overall power consumption.
Solution Approach 2:
The patent implements partial scrubbing by focusing error detection resources on modified cache lines rather than uniformly scrubbing all cache lines. This partial action approach provides sufficient error detection capability for the most vulnerable data (modified lines) while avoiding excessive scrubbing of clean lines, thus optimizing the balance between reliability and power consumption.
Data Source
AI summary
A method for minimizing soft error rates within caches by controlling a memory scrubbing rate selectively for a cache memory at an individual bank level. More specifically, the disclosure relates to maintaining a predetermined sequence and process of storing all modified information of a cache in a subset of ways of the cache, based upon for example, a state of a modified indication within status information of a cache line. A cache controller includes a memory scrubbing controller which is programmed to scrub the subset of the ways with the modified information at a smaller interval (i.e., more frequently) compared to the rest of the ways with clean information (i.e., information where the information stored within the main memory is coherent with the information stored within the cache).