Cache Memory Segmentation for Dual-Path Access Arbitration
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Solution Overview
Problem
Current cache memory systems in computer systems face inefficiencies in accessing frequently used data, leading to increased processing times for tasks like interrupt service routines and high-speed communication, as frequently used information may be evicted and retrieved from slower system memories.
Innovation Solution
A cache memory circuit is configured to store cache lines in multiple regions, allowing a control circuit to arbitrate access between processor core requests and functional circuit requests, allocating a portion as cache memory and another as memory-mapped RAM, enabling faster access and retention of frequently used data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If cache memory is used to store frequently accessed data, then access time is reduced, but cache memory capacity is limited and frequently used information may be evicted
Solution Approach 1:
The cache memory is divided into multiple regions (first region, second region, third region) with different access paths. The first region is accessible via both the first access path (fast) and second access path (slower), while the second and third regions are accessible only via the second access path. This segmentation allows frequently accessed data to be placed in the first region for fast access, while maintaining additional storage capacity in the second and third regions.
Solution Approach 2:
The first region of the cache memory serves dual purposes: it functions as both cache memory (accessible via the first access path for fast processor core access) and as system memory (accessible via the second access path for broader system access). This multi-functionality effectively increases the usable cache capacity without requiring additional physical memory resources.
2Speed
If cache memory is physically located closer to processor core with different access path, then access speed is improved, but system complexity increases due to multiple access paths and regions
Solution Approach 1:
The cache memory is segmented into multiple regions with different access characteristics. The first region has dual access paths while the second and third regions have a single access path. This segmentation allows the system to manage complexity by having simple single-path regions for less frequently accessed data and a more complex dual-path first region for frequently accessed data that needs both fast and system-wide access.
Solution Approach 2:
The system dynamically manages data placement and access based on usage patterns. The control circuit determines whether to access the first region via the fast first access path or the slower second access path based on the specific memory access request, allowing flexible adaptation to different access scenarios and optimizing performance while managing complexity.
Data Source
AI summary
An apparatus includes a control circuit and a cache memory with a plurality of regions. The control circuit receives a first and a second access request to access the cache memory. In response to determining that the first access request is from a particular processor core, and that the first access request is associated with a particular cache line in the cache memory, the control circuit stores the first access request in a cache access queue. In response to a determination that the second access request is received from a functional circuit, and that the second access request is associated with a range of a memory address space mapped to a subset of the plurality of regions, the control circuit stores the second access request in a memory access queue. The control circuit arbitrates access to the cache memory circuit between the first access request and the second access request.