Cache Memory Segmentation for Real-Time Image Processing

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Solution Overview

Problem

Bandwidth and memory issues arise in electronic devices when processing image data in real-time, particularly with increased refresh rates and pixel resolution, affecting the performance of pixel drive compensation and burn-in compensation circuitry.

Innovation Solution

Implementing a guaranteed real-time virtual channel that allocates portions of cache memory as static RAM to supplement RAM, ensuring real-time processing by prioritizing bandwidth and memory allocation for image processing operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If cache memory is used with first-come-first-served allocation, then memory utilization is flexible and high, but real-time processing cannot be guaranteed for image processing circuitry

Engineering Contradiction:
Improvereal-time processing guaranteeVSAvoidmemory allocation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The cache memory is segmented into a first portion and a second portion. The first portion is allocated to the image processing circuitry for real-time processing operations, while the second portion is allocated to other circuitry. This segmentation ensures that the image processing circuitry has dedicated cache resources guaranteed for real-time operations, eliminating the uncertainty of first-come-first-served allocation while maintaining overall system efficiency.

Inventive Principle:
Principle #1Segmentation

2Reliability

If RAM is provisioned for multiple real-time agents, then real-time processing capability is improved, but available RAM and bandwidth become insufficient

Engineering Contradiction:
Improvereal-time processing capabilityVSAvoidavailable RAM and bandwidth
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The cache memory serves multiple functions: it provides real-time processing support for image processing circuitry through the first portion, while the second portion continues to serve other circuitry needs. This multi-functional use of cache memory allows the system to support multiple real-time agents without requiring additional physical RAM, effectively resolving the bandwidth and memory quantity constraints.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Manufacturing precision

If image data processing is performed for high refresh rates and pixel resolution, then image display quality is improved, but bandwidth and memory demands increase

Engineering Contradiction:
Improveimage display qualityVSAvoidbandwidth and memory demand
Core Design Contradiction:
Manufacturing precisionVSQuantity of substance

Solution Approach 1:

The cache memory is differentially allocated to meet the specific needs of different circuitry. The first portion is optimized for image processing circuitry's real-time requirements with guaranteed bandwidth, while the second portion serves other needs. This localized quality assignment ensures that high-resolution, high-refresh-rate image processing receives dedicated resources without unnecessarily increasing overall system memory and bandwidth demands.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11875427B2Guaranteed real-time cache carveout for displayed image processing systems and methods
Publication Date: 2024.01.16 APPLE INC
  • US11875427B2 patent drawing
  • US11875427B2 patent drawing
  • US11875427B2 patent drawing

AI summary

An electronic device may include an electronic display to display an image based on processed image data. The electronic device may also include image processing circuitry to generate the processed image data based on input image data and previously determined data stored in memory. The image processing circuitry may also operate according to real-time computing constraints. Cache memory may store the previously determined data in a provisioned section of the cache memory allotted to the image processing circuitry. Additionally, a controller may manage reading and writing of the previously determined data to the provisioned section of the cache memory.