Multiple Channel Cache Memory Using SerDes and Pseudo-Multiple Port
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Solution Overview
Problem
Existing high-performance computing systems face challenges in optimizing memory access latency and bandwidth while minimizing the number of interface pins between processor and memory chips, leading to increased costs and complexity.
Innovation Solution
The proposed solution involves using a SerDes technique for the data bus and a pseudo-multiple port technique for the command/address bus to enable multiple concurrent memory channels, reducing the need for additional pins and maintaining high memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple concurrent memory channels are implemented, then memory bandwidth is improved, but the number of interface connection pins increases
Solution Approach 1:
The patent replaces the traditional parallel mechanical connection system with a serial communication system using SerDes (serializer/deserializer) technology. Instead of using multiple parallel data pins to achieve high bandwidth, the system serializes data into a single or few high-speed serial channels, fundamentally substituting the parallel-to-serial connection paradigm to reduce pin count while maintaining or improving bandwidth.
Solution Approach 2:
The patent changes the operational parameters of the memory interface by transitioning from low-speed parallel communication to high-speed serial communication. This involves changing the data transmission rate, signal encoding scheme, and timing characteristics, allowing high bandwidth to be achieved through increased clock frequency and efficient serialization rather than through increased pin count.
2Productivity
If a large cache RAM is integrated on the same silicon, then cache performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent segments the memory hierarchy by implementing multiple independent or semi-independent memory channels that can be selectively activated. Instead of requiring a single large cache RAM to handle all memory traffic, the system divides memory access into multiple channels that can operate concurrently, allowing the effective cache capacity to be achieved through coordination of smaller memory structures rather than a single large integrated cache.
Data Source
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AI summary
A high performance, low power, and cost effective multiple channel cache-system memory system is disclosed.