Cache Memory Spin Wait Power Reduction via Read Request Stalling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-processor systems, spinlock operations lead to high power consumption during spin wait loops due to continuous cache hits, where processors and cache memories operate at high speed without performing useful processes, and existing solutions either partially reduce power consumption or deteriorate spinlock performance by setting inappropriate wait times for lock variables.
Innovation Solution
A data processor design where CPUs coupled to a common memory via cache coherency temporarily stop acknowledging read requests from the cache memory during spinlock processes until predetermined conditions are met, such as snoop write hits or interrupt requests, thereby stalling pipeline execution and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If processors continuously execute spin wait loops to obtain locks, then lock acquisition speed is improved, but power consumption increases significantly
Solution Approach 1:
The patent implements periodic action by having the cache memory temporarily stop acknowledging read requests during spin wait loops, creating periodic pauses in the continuous spinning process. This reduces power consumption during the wait period while maintaining the ability to quickly acquire the lock when available, thus resolving the contradiction between fast lock acquisition and low power consumption.
2Productivity
If cache memory continuously acknowledges read requests during spin wait, then processor performance is maintained, but power consumption increases
Solution Approach 1:
The cache memory temporarily stops acknowledging read requests during spin wait loops, creating periodic inactive periods. This reduces cache memory power consumption during the wait period while maintaining processor performance by allowing the processor to quickly resume normal operation when the lock becomes available, thus resolving the contradiction between maintaining processor performance and reducing cache power consumption.
3Use of energy by stationary object
If fixed wait times are set for spinlock, then power consumption is reduced, but spinlock performance deteriorates
Solution Approach 1:
The patent implements dynamics by making the wait time adaptive rather than fixed. The cache memory temporarily stops acknowledging requests only during actual spin wait conditions, allowing the system to dynamically adjust the wait period based on real-time lock availability. This resolves the contradiction by eliminating the need for fixed wait times while maintaining both power consumption reduction and spinlock performance.
Data Source
AI summary
The present invention provides a data processor capable of reducing power consumption at the time of execution of a spin wait loop for a spinlock. A CPU executes a weighted load instruction at the time of performing a spinlock process and outputs a spin wait request to a corresponding cache memory. When the spin wait request is received from the CPU, the cache memory temporarily stops outputting an acknowledge response to a read request from the CPU until a predetermined condition (snoop write hit, interrupt request, or lapse of predetermined time) is satisfied. Therefore, pipeline execution of the CPU is stalled and the operation of the CPU and the cache memory can be temporarily stopped, and power consumption at the time of executing a spin wait loop can be reduced.