Cache Memory Architectural State Storage
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Solution Overview
Problem
Conventional processors face challenges in quickly saving and restoring architectural states during power transitions, which affects power savings and security, as existing methods either require additional hardware for faster save and restore times or compromise security by using system memory.
Innovation Solution
Implementing an 'allocate without fill' mode in cache memory to reduce storage time of architectural state data, transitioning to a conventional fill mode if interrupted, and using a hierarchical cache structure to store and restore states efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If architectural state is saved to dedicated SRAM, then save and restore times are reduced and security is improved, but additional hardware is required resulting in increased cost
Solution Approach 1:
The patent applies universality by making the cache memory serve dual purposes: storing both architectural state data during power transitions and regular processor data during normal operation. This eliminates the need for dedicated SRAM hardware while maintaining fast save/restore times and security, as the cache is already present in the processor core for general use.
Solution Approach 2:
The patent merges the architectural state storage function with the existing cache memory structure. By combining these functions into a single storage resource, the patent avoids duplicating hardware (separate SRAM) and leverages the cache's existing fast access characteristics and security properties for state preservation.
2Device complexity
If architectural state is saved to system memory, then existing memory infrastructure is used, but save and restore times increase and security decreases
Solution Approach 1:
The patent applies local quality by utilizing the cache memory's inherent fast access properties specifically for architectural state storage. The cache's proximity to the processor core and optimized access paths provide locally superior speed compared to system memory, while its existing security mechanisms protect the stored state data.
3Device complexity
If architectural state is saved to system memory, then existing memory infrastructure is used, but security decreases
Solution Approach 1:
The patent leverages the cache memory's existing security properties by making it serve dual purposes. The cache's inherent security mechanisms, designed for protecting processor data, automatically protect architectural state data when stored there, providing security without requiring separate security infrastructure.
Data Source
AI summary
A method includes storing architectural state data associated with a processing unit in a cache memory using an allocate without fill mode. A system includes a processing unit, a cache memory, and a cache controller. The cache controller is to receive architectural state data associated with the processing unit and store at least a first portion of the architectural state data in the cache memory using a first fill mode responsive to a first value of a fill mode flag and store at least a second portion of the architectural state data in the cache memory using a second fill mode responsive to a second value of a fill mode flag, wherein the first fill mode differs from the second fill mode with respect to whether previous values of the architectural state data are retrieved prior to storing the first or second portions in the cache memory.