Cache Memory Tag Storage Segmentation for Overhead Reduction
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Solution Overview
Problem
Current cache memory systems face inefficiencies in balancing data storage granularity and tag value storage overhead, particularly in managing shared and individual-tag data values, which affects access speed and energy consumption.
Innovation Solution
The implementation of a cache memory system with a plurality of blocks of bit storage circuits and control circuitry that allows for selectable modes: one for shared-tag data values and another for individual-tag data values, utilizing a tag memory to store a discriminator value indicative of individual tags, facilitating efficient access and storage through a two-stage lookup process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual tags are stored for each data value to improve tag identification precision, then measurement precision is improved, but device complexity increases due to additional tag storage overhead
Solution Approach 1:
The cache block is divided into multiple data values, and the tag storage is segmented into a shared tag portion and individual tag portions. Each data value within a cache block shares the common tag portion, while only requiring minimal individual identification bits, thereby reducing overall tag storage overhead while maintaining precise identification capability.
Solution Approach 2:
Multiple data values within a cache block share a common tag structure. The shared tag portion contains the common identification information for all data values in the block, merging the tag storage requirements and eliminating redundant tag copies, thus reducing storage overhead while preserving individual data value identifiability.
2Device complexity
If larger cache blocks are used to reduce tag overhead, then device complexity is reduced, but productivity decreases due to reduced storage granularity flexibility
Solution Approach 1:
The cache system dynamically selects between different operational modes: a first mode for processing cache blocks with shared tags (reducing tag overhead) and a second mode for cache blocks requiring individual tags (maintaining storage granularity flexibility). This dynamic mode selection allows the system to adapt to different access patterns and data characteristics, optimizing both complexity and productivity based on runtime conditions.
Solution Approach 2:
The system changes the tag storage parameter based on the cache block configuration and access patterns. By switching between shared-tag and individual-tag modes, the effective tag storage parameter is adjusted dynamically, allowing the system to optimize the balance between tag overhead reduction and storage granularity flexibility according to specific operational requirements.
3Device complexity
If shared tags are used for multiple data values to reduce storage overhead, then device complexity is reduced, but measurement precision decreases in distinguishing individual data values
Solution Approach 1:
The tag structure is segmented into a shared common portion and a minimal individual portion. The shared portion contains the common tag information that identifies the cache block, while the individual portion contains sufficient bits to distinguish between multiple data values within that block. This segmentation reduces overall tag storage compared to full individual tags while maintaining the precision needed to identify specific data values.
Solution Approach 2:
The system adds a dimensional aspect to tag storage by organizing tags hierarchically: first dimension is the shared tag portion that identifies the cache block, and the second dimension is the individual tag portion that identifies the specific data value within the block. This two-dimensional tag structure allows efficient distinction of individual data values with reduced storage overhead compared to flat individual tag storage.
Data Source
AI summary
A cache memory, such as a translation lookaside buffer cache 16, includes a plurality of blocks of bit storage circuits 26 which can operate in either a first mode to store a plurality of shared-tagged data values having a shared tag, which his stored in a tag memory 24, or in a second mode to store a plurality of individual-tag data values and respective individual tags. The tag entries within the tag memory comprise the shared tag value for a given block operating in the first mode and a composite value for a given block operating in the second mode. The composite value includes a discriminator value indicative of the respective individual tags, such as a hash value or a Bloom filter value calculated in dependence upon the individual tags, using which potential matches with the individual tags may be identified from the discriminator value.