Cache Memory Tile Coalescing for Compressed Data Bandwidth

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Solution Overview

Problem

Processing systems face inefficiencies in memory bandwidth utilization when the size of the compression atom does not match the size of the memory atom, leading to reduced performance during compressed data accesses.

Innovation Solution

A system with a cache memory that coalesces compressed data within groups of blocks in memory, optimizing storage and retrieval by aligning compressed data within contiguous memory regions to match the size of the memory atom, thereby maximizing bandwidth utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the size of the compression atom is optimized independently from the memory atom size, then the compression format can be optimized for its specific technology, but the memory bandwidth utilization decreases when the sizes do not match

Engineering Contradiction:
Improvecompression atom optimizationVSAvoidmemory bandwidth utilization
Core Design Contradiction:
Ease of manufactureVSLoss of energy

Solution Approach 1:

The patent merges the compression atom and memory atom concepts by organizing compressed data into tiles where the total size matches the memory atom size. This allows the compression format to be independently optimized while ensuring that the combined compression overhead and data fit perfectly into memory transfer units, eliminating bandwidth waste.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the organizational parameters of compressed data by introducing tiles with specific size constraints. Instead of using fixed-size compression atoms independently of memory architecture, the system adjusts the compression organization to match memory atom sizes, transforming the parameter relationship between compression and memory subsystems.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If compressed data is stored in fixed-size compression atoms that do not align with memory atom boundaries, then the compression storage is simplified, but the memory bandwidth is wasted due to transferring meaningless data

Engineering Contradiction:
Improvecompression storage organizationVSAvoidmemory bandwidth utilization
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments compressed data into tiles with specific size constraints that align with memory atom boundaries. Each tile contains compressed data plus necessary overhead, and the segmentation ensures that complete tiles are transferred together, avoiding partial transfers and wasted bandwidth while maintaining manageable storage organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by ensuring that each tile is self-contained with its own compression overhead, allowing independent processing and transfer. This local organization ensures that each memory transfer operation is efficient and complete, without requiring additional transfers for overhead data.

Inventive Principle:
Principle #3Local quality

3Quantity of substance

If the compression atom size is smaller than the memory atom size, then the compression efficiency can be improved, but the memory bandwidth is underutilized due to transferring padding data

Engineering Contradiction:
Improvecompression efficiencyVSAvoidmemory bandwidth waste
Core Design Contradiction:
Quantity of substanceVSLoss of energy

Solution Approach 1:

The patent combines multiple compression atoms into a single tile that fills the memory atom size. By merging the compression data with necessary overhead and padding within the tile structure, the system ensures that the entire memory atom is utilized effectively, transferring useful compressed data rather than wasting bandwidth on padding.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10402323B2Organizing memory to optimize memory accesses of compressed data
Publication Date: 2019.09.03 NVIDIA CORP
  • US10402323B2 patent drawing
  • US10402323B2 patent drawing
  • US10402323B2 patent drawing

AI summary

In one embodiment of the present invention a cache unit organizes data stored in an attached memory to optimize accesses to compressed data. In operation, the cache unit introduces a layer of indirection between a physical address associated with a memory access request and groups of blocks in the attached memory. The layer of indirection--virtual tiles--enables the cache unit to selectively store compressed data that would conventionally be stored in separate physical tiles included in a group of blocks in a single physical tile. Because the cache unit stores compressed data associated with multiple physical tiles in a single physical tile and, more specifically, in adjacent locations within the single physical tile, the cache unit coalesces the compressed data into contiguous blocks. Subsequently, upon performing a read operation, the cache unit may retrieve the compressed data conventionally associated with separate physical tiles in a single read operation.