Cache Memory Vector Load Buffer for Latency and Power Reduction
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Solution Overview
Problem
The existing vector processor architecture faces challenges in reducing hardware and power consumption due to increased memory latency, as the capacity of the vector load buffer must be increased to conceal memory latency, leading to higher hardware and power consumption.
Innovation Solution
Implementing a cache memory as a vector load buffer, where vector data is divided into smaller chunks and stored across multiple cache lines, allowing the cache controller to send all data to the vector processing unit once it is fully assembled, rather than sending it serially.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the capacity of the vector load buffer is increased to conceal memory latency, then the memory latency is concealed, but the hardware amount and power consumption increase
Solution Approach 1:
The patent merges the vector load buffer function with the cache memory, combining two separate components into one. The cache memory is configured to perform both traditional caching operations and vector load buffering operations, eliminating the need for a separate vector load buffer and reducing hardware amount while maintaining the ability to conceal memory latency
Solution Approach 2:
The cache memory is designed to serve multiple functions: it acts as both a traditional cache memory for scalar processors and as a vector load buffer for vector processors. This multi-functionality allows the same hardware structure to handle different types of data access patterns without requiring additional dedicated hardware
2Loss of time
If the capacity of the vector load buffer is increased to conceal memory latency, then the memory latency is concealed, but the power consumption increases
Solution Approach 1:
The patent merges the vector load buffer function with the cache memory, combining two separate components into one. The cache memory is configured to perform both traditional caching operations and vector load buffering operations, eliminating the need for a separate vector load buffer and reducing hardware amount while maintaining the ability to conceal memory latency
Solution Approach 2:
The cache memory is designed to serve multiple functions: it acts as both a traditional cache memory for scalar processors and as a vector load buffer for vector processors. This multi-functionality allows the same hardware structure to handle different types of data access patterns without requiring additional dedicated hardware
3Device complexity
If data is sent serially from cache memory to vector processing unit, then the hardware structure is simple, but the processing efficiency decreases
Solution Approach 1:
The patent implements a dynamic data transmission mechanism where the cache controller adapts its output behavior based on the completeness of data assembly. When all divisional data are available, the controller enables parallel transmission to the vector processing unit; when data are still being assembled, it maintains a waiting state. This dynamic control optimizes processing efficiency without requiring complex additional hardware
Data Source
AI summary
An apparatus includes a vector unit to process a vector data, a cache memory which includes a plurality of cache lines to store a plurality of divisional data being sent from a main memory, each of the divisional data of vector data having been divided according to a capacity of a cache line, and a cache controller to send all of the divisional data as the vector data to the vector unit after the cache lines have stored all of the divisional data including the vector data.